IDTCSPUA877ABVG8 IDT, Integrated Device Technology Inc, IDTCSPUA877ABVG8 Datasheet - Page 6

• Manufacturer Part Number: IDTCSPUA877ABVG8
• Description: IC PLL CLK DVR SDRAM 52-CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of IDTCSPUA877ABVG8

• Input: Clock
• Output: Differential
• Frequency - Max: 410MHz
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-CABGA
• Frequency-max: 410MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CSPUA877ABVG8

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
NOTES:
1. V
2. V
3. V
4. All Outputs are left open (unconnected to PCB).
5. Total I
TIMING REQUIREMENTS
NOTES:
1. The PLL will track a spread spectrum clock input.
2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications. To be used only for low speed system debug.
3. Application clock frequency is the range over which timing specifications apply.
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the
5. Will lock to input frequency as low as 30MHz at room temperature and nominal or higher supply voltage (1.8V - 1.9V).
IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
Symbol
V
levels for the power down mode.
stabilization time is also the time required for the PLL circuit to obtain phase lock of its feedback signal to its reference signal when CLK and CLK go to a logic LOW state, enters
the power-down mode, and later return to active operation. CLK and CLK may be left floating after they have been driven LOW for one complete clock cycle.
V
ID(DC) (2)
IN
ID
OD
Symbol
V
V
V
I
V
I
DDLD
V
V
OD (3)
ODL
I
IH (2)
IN (1)
I
IL (2)
DD
OH
IN
is the magnitude of the difference between the input level on CLK and the input level on CLK. The CLK and CLK V
OL
specifies the allowable DC excursion of each different output.
f
IK
CLK
t
is the magnitude of the difference between the true output level and the complementary level.
DC
t
L
DD
= I
DDQ
Input Clamp Voltage (All Inputs)
Input LOW Voltage (OE, OS, CLK, CLK)
Input HIGH Voltage (OE, OS, CLK, CLK)
Input Signal Voltage
DC Input Differential Voltage
Output Differential Voltage
Output HIGH Voltage
Output LOW Voltage
Output Disabled LOW Current
Input Current CLK, CLK
Static Supply Current (I
Dynamic Power Supply Current
(I
A
+ I
DDQ
= 0°C to +70°C
Parameter
Operating Clock Frequency
Application Clock Frequency
Input Clock Duty Cycle
Stabilization Time
ADD
and I
= F
CK
ADD
* C
)
Parameter
OE, OS, FBIN, FBIN
(4,5)
PD
* V
(4)
DDQ
DDQ
, for Cpd = (I
and I
(1,2,5)
(1,3,5)
ADD
DDQ
)
+ I
ADD
) / (F
CK
V
A
I
I
I
I
OE = L, V
A
A
A
OH
OH
OL
OL
* V
DDQ
VDD
VDD
VDD
VDD
= 100μA, V
= 9mA, V
DDQ
= -100μA, V
= -9mA, V
/V
/V
/V
/V
= 1.7V, I
) where F
DDQ
DDQ
DDQ
DDQ
ODL
= 1.7V
= Max., V
= Max., CLK and CLK = GND
= Max., CLK = 410MHz
DDQ
DDQ
= 100mV, A
I
DDQ
CK
= -18mA
DDQ
= 1.7V
is the input frequency, V
= 1.7V
6
Conditions
= 1.7V to 1.9V
= 1.7V to 1.9V
I
= 0V to V
VDD
/V
DDQ
DDQ
= 1.7V
DDQ
is the power supply, and C
IH
Min.
125
160
⎯
40
and V
COMMERCIAL TEMPERATURE RANGE
V
0.65V
DDQ
IL
Min.
-0.3
100
⎯
⎯
0.3
0.6
1.1
limits are used to define the DC LOW and HIGH
DDQ
- 0.2
PD
is the Power Dissipation Capacitance.
Typ.
⎯
⎯
⎯
⎯
⎯
⎯
Max.
410
410
60
6
V
V
0.35V
DDQ
DDQ
Max.
– 1.2
±250
±10
500
300
0.1
0.6
⎯
⎯
⎯
⎯
⎯
+ 0.3
+ 0.4
DDQ
MHz
MHz
Unit
%
μs
Unit
μA
μA
μA
mA
V
V
V
V
V
V
V