ICS9DB104BGT IDT, Integrated Device Technology Inc, ICS9DB104BGT Datasheet
ICS9DB104BGT
Specifications of ICS9DB104BGT
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ICS9DB104BGT Summary of contents
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Integrated Circuit Systems, Inc. Four Output Differential Buffer for PCI-Express Recommended Application: DB400 Intel Yellow Cover part with PCI-Express support. Output Features: • 0.7V current-mode differential output pairs • Supports zero delay buffer mode and fanout mode • ...
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Integrated Circuit Systems, Inc. Pin Description PIN # PIN NAME PIN TYPE 1 VDD PWR 2 SRC_IN IN 3 SRC_IN GND PWR 5 VDD PWR 6 DIF_1 OUT 7 DIF_1# OUT 8 OE_1 IN 9 DIF_2 OUT 10 ...
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Integrated Circuit Systems, Inc. General Description ICS9DB104 follows the Intel DB400 Differential Buffer Specification. This buffer provides four SRC clocks for PCI-Express, next generation I/O devices. ICS9DB104 is driven by a differential input pair from a CK409/CK410 main clock generator, ...
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Integrated Circuit Systems, Inc. Absolute Max Symbol Parameter VDD_A 3.3V Core Supply Voltage VDD_In 3.3V Logic Supply Voltage V Input Low Voltage IL V Input High Voltage IH Ts Storage Temperature Tambient Ambient Operating Temp Tcase Case Temperature Input ESD ...
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Integrated Circuit Systems, Inc. Electrical Characteristics - DIF 0.7V Current Mode Differential Pair 70° 3.3 V +/-5%; C =2pF PARAMETER SYMBOL Current Source Output Zo Impedance Voltage High VHigh Voltage ...
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Integrated Circuit Systems, Inc. General SMBus serial interface information for the ICS9DB104 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address DC • ICS clock will acknowledge • Controller (host) sends the ...
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Integrated Circuit Systems, Inc. SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD) Byte 0 Pin # Name - Bit 7 - SRC_Stop# drive Bit 6 Bit Bit 4 Bit 3 - Bit 2 - PLL_BW# adjust Bit ...
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Integrated Circuit Systems, Inc. SMBus Table: Output Control Register Byte 3 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: Vendor & Revision ID Register Byte 4 Pin ...
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Integrated Circuit Systems, Inc. PD# The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting off the input clock or power to insure an orderly shutdown. PD ...
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Integrated Circuit Systems, Inc. SRC_STOP# The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced ...
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Integrated Circuit Systems, Inc. SRC_STOP_3 (SRC_Stop = Driven Tristate) SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) SRC_STOP_4 (SRC_Stop = Tristate Tristate) SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) ...
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Integrated Circuit Systems, Inc INDEX INDEX AREA AREA Ordering Information ICS9DB104yFLxT Example: ICS XXXX 0767E—12/14/07 (Not recommended for new designs) c SYMBOL L ...
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Integrated Circuit Systems, Inc INDEX INDEX AREA AREA aaa Ordering Information ICS9DB104yGLxT Example: ICS XXXX 0767E—12/14/07 (Not recommended for new designs) c SYMBOL ...
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Integrated Circuit Systems, Inc. Revision History Rev. Issue Date Description D 10/26/05 Updated LF Ordering Information LF. E 12/14/07 Updated SMBus serial Interface Information. 0767E—12/14/07 (Not recommended for new designs) 14 ICS9DB104 Page # 12 ...