ICS950201AFLFT IDT, Integrated Device Technology Inc, ICS950201AFLFT Datasheet - Page 12

• Manufacturer Part Number: ICS950201AFLFT
• Description: IC TIMING CTRL HUB P4 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS950201AFLFT

• Input: Crystal
• Output: Clock
• Frequency - Max: 200MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 950201AFLFT

PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# Functionality
IDT
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising
edge.
ICS950201
Programmable Timing Control Hub
TM
C
Programmable Timing Control Hub
P
U
_
S
0
1
T
O
CPU_STOP#
PCI_F[2:0] 33MHz
P
PCI[6:0] 33MHz
#
PCI_STOP#
CPUC
CPUT
i
e r
N
C
* f
r o
P
U
m
TM
M
T
l a
for P4
TM
u
t l
for P4
Assertion of CPU_STOP# Waveforms
TM
Assertion of PCI_STOP# Waveforms
tsu
TM
N
C
F
r o
P
o l
U
m
t a
C
l a
12
2
C configuration to be stoppable via
460J—01/25/10