ICS97ULP877BH IDT, Integrated Device Technology Inc, ICS97ULP877BH Datasheet - Page 6

• Manufacturer Part Number: ICS97ULP877BH
• Description: IC CLOCK DRIVER 1.8V LP 52-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of ICS97ULP877BH

• Input: Clock
• Output: SSTL-18
• Frequency - Max: 410MHz
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-BGA
• Frequency-max: 410MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 97ULP877BH

ICS97ULP877B
NOTE: The PLL must be able to handle spread spectrum induced skew.
NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not
required to meet the other timing parameters. (Used for low speed system debug.)
NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters.
NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal, within the value specificied by the Static Phase Offset ( t
normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock
of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode
and later return to active operation. CK and CK may be left floating after they have been driven low for one
complete clock cycle.
0981C—04/05/05
T
Max clock frequency
Application Frequency
Range
Input clock duty cycle
CLK stabilization
Timing Requirements
A
= 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V + /- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
freq
freq
T
d
STAB
tin
App
op
1.8V+0.1V @ 25°C
1.8V+0.1V @ 25°C
CONDITIONS
6
MIN
160
95
40
(
Æ ), after power-up.
MAX
410
410
60
15
UNITS
MHz
MHz
µs
%
During