ICS950211BFLF IDT, Integrated Device Technology Inc, ICS950211BFLF Datasheet

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ICS950211BFLF

Manufacturer Part Number
ICS950211BFLF
Description
IC TIMING CTRL HUB P4 56-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Timing Control Hubr
Datasheet

Specifications of ICS950211BFLF

Input
Crystal
Output
Clock
Frequency - Max
205MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-SSOP
Frequency-max
205MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
950211BFLF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS950211BFLFT
Manufacturer:
ICS
Quantity:
20 000
Recommended Application:
Brookdale and Brookdale -G chipset with P4 processor.
Output Features:
Features/Benefits:
Key Specifications:
Block Diagram
0465E—05/17/05
Vtt_PWRGD#
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (4:0)
3 - Pairs of differential CPU clocks (differential current mode)
5 - 3V66 @ 3.3V
10 - PCI @ 3.3V
2 - 48MHz @ 3.3V fixed
1 - REF @ 3.3V, 14.318MHz
1 - VCH/3V66 @ 3.3V, 48 MHz or 66.6 MHz
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
Uses external 14.318MHz crystal.
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
WDEN
SDATA
SCLK
PD#
X2
X1
Integrated
Circuit
Systems, Inc.
2
Spectrum
C Index read/write and block read/write operations.
Spread
Control
Config.
XTAL
Logic
OSC
PLL1
Reg.
PLL2
Programmable Timing Control Hub™ for P4™
DIVDER
DIVDER
DIVDER
3V66
CPU
PCI
Stop
Stop
3
3
7
3
5
PCICLK_F (2:0)
48MHz_USB
PCICLK (6:0)
3V66 (5:2, 0)
I REF
48MHz_DOT
3V66_1/VCH_CLK
REF
CPUCLKT (2:0)
CPUCLKC (2:0)
For additional frequency selections please refer to Byte 0.
* For 950211BF version, this frequency is 166.66MHz.
Frequency Table
F
Power Groups
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz
1
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*WDEN/PCICLK0
1. These outputs have 2X drive strength.
** these inputs have 120K internal pull-down
4
* Internal Pull-up resistor of 120K to VDD
*Vtt_PWRGD#
1
1
56-Pin 300-mil SSOP & 240-mil TSSOP
PCICLK_F0
PCICLK_F1
PCICLK_F2
F
to GND
VDD3V66
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
VDDREF
VDDPCI
VDDPCI
3V66_2
3V66_3
3V66_4
3V66_5
3
VDDA
*PD
GND
GND
GND
GND
GND
F
X1
X2
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
#
2
Pin Configuration
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
F
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
0
S
1
1
1
1
1
1
1
1
1
F
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
C
1
2
1
1
1
1
1
1
1
1
1
2
1
1
1
6
P
M
0
0
0
3
0
0
0
1
1
2
3
3
7
8
9
6
U
0
0
3
0
5
9
4
7
7
0
2
5
0
0
0
6 .
H
C
0 .
0 .
3 .
9 .
0 .
0 .
0 .
0 .
0 .
0 .
5 .
0 .
0 .
0 .
0 .
* 6
z
L
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
K
6
6
6
6
6
7
7
7
7
7
7
7
5
6
6
3
7
REF
FS1
FS0
CPU_STOP#*
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTSEL0*
I REF
GND
FS2
48MHz_USB/FS3**
48MHz_DOT
AVDD48
GND
3V66_1/VCH_CLK/FS4**
PCI_STOP#*
3V66_0
VDD
GND
SCLK
SDATA
M
6
6
6
6
7
0
2
6
8
2
4
0
6
0
3
V
5
H
6 .
6 .
6 .
6 .
2 .
0 .
6 .
0 .
0 .
8 .
2 .
0 .
6 .
0 .
3 .
7 .
6
1
ICS950211
z
6
6
6
6
6
7
0
7
0
0
6
9
0
7
0
3
1
P
3
3
3
3
3
3
3
3
3
3
3
3
3
2
3
3
C
M
3
3
3
3
3
5
6
8
9
6
7
7
5
8
0
1
C I
H
3 .
3 .
3 .
3 .
6 .
0 .
3 .
0 .
0 .
4 .
1 .
8 .
0 .
3 .
0 .
6 .
z
L
3
3
3
3
3
0
3
0
0
3
4
9
0
3
0
7
K

Related parts for ICS950211BFLF

ICS950211BFLF Summary of contents

Page 1

Integrated Circuit Systems, Inc. Programmable Timing Control Hub™ for P4™ Recommended Application: Brookdale and Brookdale -G chipset with P4 processor. Output Features: • Pairs of differential CPU clocks (differential current mode) • 3V66 @ 3.3V • ...

Page 2

Integrated Circuit Systems, Inc. General Description The ICS950211 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR memory. It provides all necessary clock signals for such a system. The ICS950211 is ...

Page 3

Integrated Circuit Systems, Inc. Maximum Allowed Current ...

Page 4

Integrated Circuit Systems, Inc. General I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ...

Page 5

Integrated Circuit Systems, Inc. Byte 0: Functionality and frequency select register (Default= ...

Page 6

Integrated Circuit Systems, Inc. Byte 1: Output Control Register (1 = enable disable ...

Page 7

Integrated Circuit Systems, Inc. Asynchronous Frequency Control Table Byte 4 Byte 3 3V66 [0:3] Bit 7 Bit 66.01 MHz 0 1 75.44 MHz 1 0 66.66 MHz 1 1 88.01 MHz Byte 5: Programming Edge Rate (1 ...

Page 8

Integrated Circuit Systems, Inc. Byte 8: Byte Count Read Back Register ...

Page 9

Integrated Circuit Systems, Inc. Byte 12: VCO Frequency N Divider (VCO divider) Control Register ...

Page 10

Integrated Circuit Systems, Inc. Byte 16: Output Divider Control Register ...

Page 11

Integrated Circuit Systems, Inc. Byte 20: Group Skew Control Register ...

Page 12

Integrated Circuit Systems, Inc. Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs ...

Page 13

Integrated Circuit Systems, Inc. Electrical Characteristics - CPUCLK 70° 3.3 V +/-5%; (unless otherwise stated PARAMETER SYMBOL Current Source Z O Output Impedance Output High Voltage V OH Output High Current I ...

Page 14

Integrated Circuit Systems, Inc. Electrical Characteristics - 3V66 70° 3.3 V +/-5 PARAMETER SYMBOL Output Frequency Output Impedance R DSP1 Output High Voltage V OH1 Output Low ...

Page 15

Integrated Circuit Systems, Inc. Electrical Characteristics - REF 70° 3.3 V +/-5%; C =10-20 pF (unless otherwise stated PARAMETER SYMBOL Output Frequency Output Impedance R DSP1 Output High ...

Page 16

Integrated Circuit Systems, Inc. Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on ...

Page 17

Integrated Circuit Systems, Inc. All 3V66 clocks are pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI ...

Page 18

Integrated Circuit Systems, Inc. PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low ...

Page 19

Integrated Circuit Systems, Inc INDEX INDEX AREA AREA 45° 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C 300 mil SSOP Package ...

Page 20

Integrated Circuit Systems, Inc INDEX INDEX AREA AREA 240 mil TSSOP Package Ordering Information ICS950211yGLF-T Example: ICS XXXX y G LF- T 0465E—05/17/05 56-Lead 6.10 mm. Body, ...

Page 21

Integrated Circuit Systems, Inc. Revision History Rev. Issue Date Description 1. Updated Description on Byte 13. E 5/17/2005 2. Updated LF Ordering Information from "Lead Free" to "RoHS Compliant". 0465E—05/17/05 21 ICS950211 Page # 9,19-20 ...

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