ICS93776AFT IDT, Integrated Device Technology Inc, ICS93776AFT Datasheet
ICS93776AFT
Specifications of ICS93776AFT
Related parts for ICS93776AFT
ICS93776AFT Summary of contents
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Integrated Circuit Systems, Inc. Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: DDR Zero Delay Clock Buffer Product Description/Features: • Low skew, low jitter PLL clock driver • Max frequency supported = 266MHz (DDR 533) 2 • ...
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ICS93776 Pin Descriptions PIN # PIN NAME PIN TYPE DESCRIPTION 1 DDRC0 OUT 2 DDRT0 OUT 3 VDD PWR 4 DDRT1 OUT 5 DDRC1 OUT 6 GND PWR 7 SCLK IN 8 CLK_INT IN 9 CLK_INC IN 10 VDDA PWR ...
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Absolute Maximum Ratings Supply Voltage (VDD & AVDD -0.5V to 3.6V Logic Inputs . . . . . . . . . . . . . . . . . ...
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ICS93776 Timing Requirements 70°C; Supply Voltage PARAMETER SYMBOL 1 Operating Clock Frequency 1 Input Clock Duty Cycle 1 Clock Stabilization 1. Guaranteed by design, not 100% tested in production. Switching Characteristics T = ...
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General SMBus serial interface information How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D4 • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS ...
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ICS93776 Bytes are reseved power up default = 1. This allows operation with main clock. BYTE Affected Pin 0 Pin # Name Bit DDR0(T&C) Bit DDR1(T&C) Bit Bit ...
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INDEX INDEX AREA AREA 209 mil SSOP Ordering Information ICS93776yFLF-T Example: ICS XXXX y F LF- T 0793A—03/08/05 c SYMBOL ...
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ICS93776 Revision History Rev. Issue Date Description N/A 8/12/2004 Updated I2c N/A 8/20/2004 Updated I2c 0793A—03/08/05 8 Page # 6 6 ...