ICS9DB106BGLF IDT, Integrated Device Technology Inc, ICS9DB106BGLF Datasheet
ICS9DB106BGLF
Specifications of ICS9DB106BGLF
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ICS9DB106BGLF Summary of contents
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Six Output Differential Buffer for PCIe Gen 2 Description The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter ...
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Six Output Differential Buffer for PCIe Gen 2 Pin Configuration Power Groups Pin Number VDD GND 7, 13, 16, 22 8,21 TBD TBD N Analog VDD & GND for PLL core Six Output Differential Buffer for ...
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Six Output Differential Buffer for PCIe Gen 2 Pin Description PIN # PIN NAME 1 PLL_BW 2 CLK_INT 3 CLK_INC 4 **CLKREQ1# 5 PCIEXT0 6 PCIEXC0 7 VDD 8 GND 9 PCIEXT1 10 PCIEXC1 11 PCIEXT2 12 PCIEXC2 13 ...
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Six Output Differential Buffer for PCIe Gen 2 Electrical Characteristics - Absolute Maximum Ratings PARAMETER 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Input High Voltage Storage Temperature Junction Temperature Input ESD protection ...
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Six Output Differential Buffer for PCIe Gen 2 Electrical Characteristics - Clock Input Parameters Supply Voltage VDD = 3.3 V +/-5% COM IND; PARAMETER SYMBOL Input High Voltage - V IHDIF DIF_IN Input Low ...
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Six Output Differential Buffer for PCIe Gen 2 Electrical Characteristics - PCIEX 0.7V Current Mode Differential Outputs 3.3 V +/-5%; C COM IND DD PARAMETER SYMBOL Current Source Output Impedance Voltage ...
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Six Output Differential Buffer for PCIe Gen 2 Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt Down Device Differential ...
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Six Output Differential Buffer for PCIe Gen 2 Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm 0.45v 0.22v 1.08 0.58 0.28 0.6 0.80 0.40 0.6 0.60 0.3 1.2 R1a = R1b = R1 ...
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Six Output Differential Buffer for PCIe Gen 2 General SMBus serial interface information for the 9DB106 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D4 • IDT clock will acknowledge ...
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Six Output Differential Buffer for PCIe Gen 2 SMBusTable: Device Control Register, READ/WRITE ADDRESS (D4/D5) Byte 0 Pin # Name - SW_EN Bit 7 Bit 6 - Bit Bit 4 Bit Bit 2 ...
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Six Output Differential Buffer for PCIe Gen 2 SMBusTable: DEVICE ID Byte 4 Pin # Name - Bit 7 Bit 6 - Bit Bit 4 - Bit 3 Bit 2 - Bit Bit ...
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Six Output Differential Buffer for PCIe Gen 2 Six Output Differential Buffer for PCIe Gen 2 ® IDT 209 mil SSOP In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A -- 2. 1.65 1.85 b 0.22 ...
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Six Output Differential Buffer for PCIe Gen INDEX INDEX AREA AREA aaa Ordering Information Part / Order Number Shipping Packaging 9DB106BFLF Tubes 9DB106BFLFT Tape and ...
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Six Output Differential Buffer for PCIe Gen 2 Revision History Rev. Originator Issue Date Description 1. Changed Output to Output skew from 30ps to 45ps. 2. Changed PLL mode jitter from 40ps to 35ps. 3. Changed Bypass mode additive ...