ICS950220AFLFT IDT, Integrated Device Technology Inc, ICS950220AFLFT Datasheet

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ICS950220AFLFT

Manufacturer Part Number
ICS950220AFLFT
Description
IC TIMING CTRL HUB P4 48-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Timing Control Hubr
Datasheet

Specifications of ICS950220AFLFT

Input
Crystal
Output
Clock
Frequency - Max
200MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Frequency-max
200MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
950220AFLFT
Vtt_PWRGD#
Recommended Application:
CK-408 clock for Intel
Output Features:
Features/Benefits:
Key Specifications:
Block Diagram
0467G—03/02/07
MULTSEL0
SEL24_48
FS (4:0)
WDEN
SDATA
3 - Pairs of differential CPU clocks @ 3.3V
3 - 3V66 @ 3.3V
9 - PCI @ 3.3V
2 - 48MHz @ 3.3V fixed
1 - 24_48MHz @ 3.3V, 48MHz, 24Mhz or 66MHz
1 - REF @ 3.3V, 14.318MHz
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
operations.
Uses external 14.318MHz crystal.
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
SCLK
PD#
X2
X1
Integrated
Circuit
Systems, Inc.
Spectrum
2
Spread
Control
Config.
XTAL
C Index read/write and block read/write
OSC
PLL1
Logic
Reg.
PLL2
Programmable Timing Control Hub™ for P4™
®
845 chipset.
DIVDER
DIVDER
/2
CPU
PCI
DIVDER
3V66
3
3
7
3
48MHz_USB
3V66 (3:1)
PCICLK (6:0)
I REF
Reset#
48MHz_DOT
3V66_0/24_48MHZ#
REF
CPUCLKC (2:0)
CPUCLKT (2:0)
1
*WDEN/PCICLK0
Frequency Table
Pin Configuration
1. These outputs have 2X drive strength.
** these inputs have 120K internal pull-down
1
For additional frequency selections please refer to Byte 0.
Power Groups
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz
* Internal Pull-up resistor of 120K to VDD
F
1
**FS1/PCICLK8
*FS0/PCICLK7
S
0
1
1
1
to GND
4
VDD3V66
VDDREF
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
#RESET
VDDPCI
VDDPCI
F
3V66_1
3V66_2
3V66_3
S
0
0
1
1
VDDA
GND
GND
GND
GND
3
X1
X2
F
48-Pin 300-mil SSOP
S
0
0
1
1
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
F
0
0
S
1
1
1
F
S
0
1
1
1
0
C
2
1
1
P
6
M
0
0
3
U
6
0
3
0
H
6 .
C
0 .
0 .
3 .
z
7
L
0
0
3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
K
6
6
6
6
3
M
REF/FS2**
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTISEL0*
I REF
GND
48MHz_USB/FS3**
48MHz_DOT/SEL_24_48*
AVDD48
GND
3V66_0/24_48MHZ#/FS4**
VDD3V66
GND
SCLK
SDATA
Vtt_PWRGD/PD#*
GND
6
6
6
6
V
ICS950220
H
6 .
6 .
6 .
6 .
6
z
6
7
7
7
7
P
1
3
3
3
3
C
M
3
3
3
3
C I
H
3 .
3 .
3 .
3 .
L
z
3
3
4
3
K

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ICS950220AFLFT Summary of contents

Page 1

Integrated Circuit Systems, Inc. Programmable Timing Control Hub™ for P4™ Recommended Application: ® CK-408 clock for Intel 845 chipset. Output Features: • Pairs of differential CPU clocks @ 3.3V • 3V66 @ 3.3V • ...

Page 2

Integrated Circuit Systems, Inc. General Description The ICS950220 is a single chip clock solution for desktop designs using the Intel 845 chipset with PC133 or DDR memory. It provides all necessary clock signals for such a system. The ICS950220 is ...

Page 3

Integrated Circuit Systems, Inc. Maximum Allowed Current ...

Page 4

Integrated Circuit Systems, Inc. General SMBus serial interface information How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends the begining byte location ...

Page 5

Integrated Circuit Systems, Inc. Byte 0: Functionality and frequency select register (Default= ...

Page 6

Integrated Circuit Systems, Inc. Byte 1: Output Control Register (1 = enable disable ...

Page 7

Integrated Circuit Systems, Inc. Byte 5: Programming Edge Rate (1 = enable disable ...

Page 8

Integrated Circuit Systems, Inc. Byte 9: Watchdog Timer Count Register ...

Page 9

Integrated Circuit Systems, Inc. Byte 13: Spread Spectrum Control Register ...

Page 10

Integrated Circuit Systems, Inc. Byte 17: Output Divider Control Register ...

Page 11

Integrated Circuit Systems, Inc. Byte 20: Group Skew Control Register ...

Page 12

Integrated Circuit Systems, Inc. Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs ...

Page 13

Integrated Circuit Systems, Inc. Electrical Characteristics - CPU 0.7V Current Mode Differential Pair 70° 3.3 V +/-5 PARAMETER SYMBOL Current Source Output 1 Zo Impedance Voltage High VHigh Voltage Low ...

Page 14

Integrated Circuit Systems, Inc. Electrical Characteristics - PCICLK 70°C; VDD=3.3V +/-5 PARAMETER SYMBOL F Output Frequency Output Impedance R DSP1 Output High Voltage V OH Output Low Voltage V OL Output High Current I ...

Page 15

Integrated Circuit Systems, Inc. Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB 70°C; VDD=3.3V +/-5 PARAMETER SYMBOL F Output Frequency O1 Output Impedance R DSP1 Output High Voltage V OH Output Low Voltage ...

Page 16

Integrated Circuit Systems, Inc. Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on ...

Page 17

Integrated Circuit Systems, Inc. All 3V66 clocks are pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI ...

Page 18

Integrated Circuit Systems, Inc. PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low ...

Page 19

Integrated Circuit Systems, Inc INDEX INDEX AREA AREA 45° 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C 300 mil SSOP Package ...

Page 20

Integrated Circuit Systems, Inc. Revision History Rev. Issue Date Description F 7/28/2005 Added LF Ordering Information. G 3/2/2007 Updated Electrical Characteristics CPU Skew spec. 0467G—03/02/07 20 ICS950220 Page # 19 13 ...

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