ICS9248DF-39 IDT, Integrated Device Technology Inc, ICS9248DF-39 Datasheet
ICS9248DF-39
Specifications of ICS9248DF-39
Available stocks
Related parts for ICS9248DF-39
ICS9248DF-39 Summary of contents
Page 1
Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers for PENTIUM/Pro General Description The ICS9248-39 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are ...
Page 2
ICS9248-39 Pin Descriptions ...
Page 3
Mode Pin - Power Management Input Control Functionality V 1,2,3 = 3.3V±5%, ...
Page 4
ICS9248-39 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = ± ...
Page 5
Byte 1: CPU, Active/Inactive Register (1 = enable disable ...
Page 6
ICS9248-39 Byte 4: Reserved Active/Inactive Register (1 = enable disable ...
Page 7
Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . ...
Page 8
ICS9248-39 Electrical Characteristics - CPUCLK 70° 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH2B Output Low Voltage V OL2B Output High Current I OH2B Output Low Current I OL2B ...
Page 9
Electrical Characteristics - SDRAM 70° 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH3 Output Low Voltage V OL3 Output High Current I OH3 Output Low Current I OL3 1 ...
Page 10
ICS9248-39 Electrical Characteristics - 24MHz, 48MHz, REF(0: 70° 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH5 Output Low Voltage V OL5 Output High Current I OH5 Output Low Current ...
Page 11
General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock ...
Page 12
ICS9248-39 CPU_STOP# Timing Diagram CPU_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-39. The minimum that the CPU clock is enabled ...
Page 13
PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-39 used to turn off the PCICLK (0:4) clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-39 internally. The minimum that the PCICLK (0:4) clocks are ...
Page 14
ICS9248-39 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9248- 39 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present ...
Page 15
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Notes: 1 All clock ...
Page 16
ICS9248-39 TOP VIEW A 2 SEE DETAIL “A” ...