ICS9248BF-138 IDT, Integrated Device Technology Inc, ICS9248BF-138 Datasheet

ICS9248BF-138

Manufacturer Part Number

ICS9248BF-138

Description

IC FREQ GENERATOR/BUFFER 48-SSOP

Manufacturer

IDT, Integrated Device Technology Inc

Type

Frequency Generatorr

Datasheet

1.ICS9248BF-138LFT.pdf (12 pages)

Specifications of ICS9248BF-138

Input

Crystal

Output

Clock

Frequency - Max

200MHz

Voltage - Supply

3.135 V ~ 3.465 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

48-SSOP

Frequency-max

200MHz

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

9248BF-138

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

ICS9248BF-138

Manufacturer:

ICS

Quantity:

225

Current page: 1 of 12
Download datasheet (136Kb)

Frequency Generator & Integrated Buffers for Celeron & PII/III

Recommended Application:

810/810E and Solano type chipset.

Output Features:

•

Features:

•

Skew Specifications:

•

Block Diagram

SEL24_48#

0342C—08/26/03

FS[4:0]

SDATA

SCLK

2- CPUs @ 2.5V

9 - SDRAM @ 3.3V, including 1 free running

7 - PCICLK @ 3.3V

1 - IOAPIC @ 2.5V,

3 - 3V66MHz @ 3.3V

2 - 48MHz, @ 3.3V fixed.

1 - 24/48MHz, @3.3V selectable by I

1 - REF @v3.3V, 14.318MHz.

Up to 200MHz frequency support

Support FS0-FS4 strapping status bit for I

back.

Support power management: Through Power down

Mode from I

Spread spectrum for EMI control ( ± 0.25% center).

Uses external 14.318MHz crystal

CPU – CPU: <175ps

SDRAM - SDRAM: < 250ps

3V66 – 3V66: <175ps

PCI – PCI: <500ps

For group skew specifications, please refer to group

timing relationship.

PD#

XTAL

OSC

Spectrum

PLL2

Spread

Control

Config.

PLL1

Logic

Reg.

C programming.

Integrated

Circuit

Systems, Inc.

DIVDER

SDRAM

DIVDER

IOAPIC

CPU

3V66

PCI

/ 2

48MHz [1:0]

24_48MHz

SDRAM [7:0]

SDRAM_F

IOAPIC

PCICLK [6:0]

3V66 [2:0]

CPUCLK [1:0]

REF0

C read

Functionality

Additional frequencies selectable through I

*SEL24_48#/REF0

**FS1/PCICLK1

*FS0/PCICLK0

GND3V66

VDD3V66

GNDREF

PCICLK2

PCICLK3

PCICLK4

PCICLK5

PCICLK6

VDDREF

GNDPCI

VDDPCI

* These inputs have a 120K pull up to VDD.

1 These are double strength.

3V66-0

3V66-1

3V66-2

SDATA

SCLK

PD#

These inputs have a 120K pull down to GND.

48-Pin 300mil SSOP

Pin Configuration

(

6 1

0 1

3 1

2 1

3 1

2 1

. 6

. 8

. 1

. 0

. 6

. 0

. 3

. 7

. 3

. 7

. 0

. 3

. 7

. 0

7 6

7 8

7 6

4 3

0 0

7 6

0 0

0 3

0 0

3 3

3 7

3 3

0 0

3 3

3 7

3 3

0 0

) z

6 1

2 1

6 1

2 1

(

0 1

3 1

2 1

0 1

. 0

. 5

. 6

. 0

. 3

. 7

. 0

. 3

. 7

. 3

. 7

. 0

. 3

0 0

7 6

0 0

0 3

0 0

0 3

0 0

0 3

0 0

3 3

3 7

3 3

) z

ICS9248-138

(

C programming.

. 0

. 3

. 6

. 8

. 1

. 6

. 8

. 1

. 6

. 8

. 0

. 6

. 8

. 0

0 0

4 3

7 6

7 8

7 6

4 3

7 6

7 8

7 6

4 3

7 6

7 8

7 6

0 0

7 6

7 8

7 6

0 0

6 6

) z

VDDLAPIC

IOAPIC

VDDLCPU

CPUCLK0

CPUCLK1

GNDLCPU

GNDSDR

SDRAM0

SDRAM1

SDRAM2

VDDSDR

SDRAM3

SDRAM4

SDRAM5

GNDSDR

SDRAM6

SDRAM7

SDRAM_F

VDDSDR

GND48

24_48MHz/FS2**

48MHz/FS3*

48MHz/FS4*

VDD48

(

. 0

. 1

. 5

. 0

C I

. 3

. 4

. 3

. 4

. 3

. 4

. 3

. 4

0 0

7 6

3 3

3 4

3 3

6 6

3 3

3 4

3 3

6 6

3 3

3 4

3 3

0 0

3 3

3 4

3 3

0 0

) z

(

. 0

. 6

. 7

. 6

. 7

. 6

. 7

. 5

. 6

. 7

. 5

0 0

4 8

7 6

2 7

6 1

3 8

7 6

2 7

7 1

4 8

7 6

2 7

7 1

0 0

7 6

2 7

7 1

0 0

) z

C I

Related parts for ICS9248BF-138

ICS9248BF-138 Summary of contents

Page 1

Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers for Celeron & PII/III Recommended Application: 810/810E and Solano type chipset. Output Features: • 2- CPUs @ 2.5V • SDRAM @ 3.3V, including 1 free running • ...

Page 2

ICS9248-138 General Description The ICS9248-138 is the single chip clock solution for designs using the 810/810E and Solano style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I 10dB. This simplifies ...

Page 3

Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = ...

Page 4

ICS9248-138 Byte 1: SDRAM Control Register (1= enable disable ...

Page 5

Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . 5.5 V I/O Supply Voltage . . . . . . . . . ...

Page 6

ICS9248-138 Electrical Characteristics - CPU 70° 2.5 V +/-5 DDL PARAMETER SYMBOL 1 Output Impedance R DSP2B 1 Output Impedance R DSN2B Output High Voltage V OH2B Output Low Voltage V OL2B ...

Page 7

Electrical Characteristics - IOAPIC 70°C;V = 2.5 V +/-5 DDL PARAMETER SYMBOL 1 Output Impedance R DSP4B 1 Output Impedance R DSN4B Output High Voltage V OH4\B Output Low Voltage V OL4B Output High ...

Page 8

ICS9248-138 Electrical Characteristics - PCI 70° 3.3 V +/-5 PARAMETER SYMBOL 1 Output Impedance R DSP1 1 Output Impedance R DSN1 Output High Voltage V OH1 Output Low Voltage V OL1 ...

Page 9

General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock ...

Page 10

ICS9248-138 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9248- 138 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present ...

Page 11

PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD asynchronous active low input. This signal needs to be synchronized ...

Page 12

ICS9248-138 INDEX INDEX AREA AREA 45° 45° .10 (.004) C .10 (.004) C Ordering Information 9248yF-138 Example: XXXX PPP - T ...

Related keywords

ics9248
ics9250bf
ics9250cf
ICS9248BF-138 datasheet
ICS9248BF-138 data sheet
ICS9248BF-138 pdf datasheet
ICS9248BF-138 component
ICS9248BF-138 part
ICS9248BF-138 distributor
ICS9248BF-138 RoHS
ICS9248BF-138 datasheet download