ICS9ERS3125BKILFT IDT, Integrated Device Technology Inc, ICS9ERS3125BKILFT Datasheet - Page 17

• Manufacturer Part Number: ICS9ERS3125BKILFT
• Description: IC EMBEDDED PC MAIN CLK 56VQFN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS9ERS3125BKILFT

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT
Byte 10 Output Control Register
Byte 11 iAMT/CPU2 Control Register
Byte 12 Byte Count Register
Byte 13 Single Ended Output Slew Rate Control Register
Byte 14 Reserved
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
ICS9ERS3125
Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
TM
/ICS
TM
27_SEL Latch Readback
Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
CPU1 Stop Enable
CPU0 Stop Enable
CPU2 Stop Enable
CPU2_AMT_EN
CPU1_AMT_EN
PCI4 STOP EN
PCI3 STOP EN
PCI2 STOP EN
PCI1 STOP EN
PCI0 STOP EN
Reserved
27M_FIX
27M_FIX
27M_SS
27M_SS
Name
Name
Name
Name
Name
BC5
BC4
BC3
BC2
BC1
BC0
REF
REF
Allows control of PCI4 with assertion of PCI_STOP#
Allows control of PCI3 with assertion of PCI_STOP#
Allows control of PCI2 with assertion of PCI_STOP#
Allows control of PCI1 with assertion of PCI_STOP#
Allows control of PCI0 with assertion of PCI_STOP#
Enables control of CPU1 with CPU_STOP#
Enables control of CPU0 with CPU_STOP#
Enables control of CPU2 with CPU_STOP#
M1 mode clk enable, only if ITP_EN=1
Read Back byte count register,
Readback of 27_Select latch
M1 mode clk enable
Slew Rate Control
Slew Rate Control
Slew Rate Control
max bytes = 32
Description
Description
Description
Description
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
17
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
Dot96/ LCD_SS /SE
Free Running
Free Running
Free Running
Free running
Free running
Free running
Free running
Free running
10 = 2.0 V/ns
10 = 2.0 V/ns
10 = 2.0 V/ns
00 = Hi-Z
00 = Hi-Z
00 = Hi-Z
Disable
Disable
0
0
0
0
0
-
-
-
-
-
-
-
PCI_STOP# assertion
PCI_STOP# assertion
PCI_STOP# assertion
PCI_STOP# assertion
PCI_STOP# assertion
SRC0/ 27MHz
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
Stops with
Stops with
Stops with
Stops with
Stops with
Stoppable
Stoppable
Stoppable
Enable
Enable
1
1
1
1
1
-
-
-
-
-
-
-
Datasheet
1612—08/19/09
27_SEL latch
Default
Default
Default
Default
Default
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
0