ICS93716AG IDT, Integrated Device Technology Inc, ICS93716AG Datasheet - Page 6

• Manufacturer Part Number: ICS93716AG
• Description: IC DDR PLL CLOCK DRIVER 28-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of ICS93716AG

• Input: Clock
• Output: Clock
• Frequency - Max: 233MHz
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Frequency-max: 233MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 93716AG

Notes:
1.
2.
3.
4.
0420H—09/10/08
T
Max clock frequency
Application Frequency
Range
Input clock duty cycle
CLK stabilization
T
Low-to high level
propagation delay time
High-to low level propagation
delay time
Duty Cycle
Input clock slew rate
Cycle to Cycle Jitter
Cycle to Cycle Jitter
Phase error
Output to Output Skew
Rise Time, Fall Time
Timing Requirements
Switching Characteristics
A
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R
Refers to transition on noninverting output in PLL bypass mode.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t
the cycle (t
Switching characteristics guaranteed for application frequency range.
Static phase offset shifted by design.
3
PARAMETER
PARAMETER
c
) decreases as the frequency goes up.
1
1
3
t
SYMBOL
SYMBOL
(phase error)
t
t
freq
cyc
cyc
freq
T
t
t
t
t
t
PLH
PHL
DC
d
STAB
skew
r
sl(I)
, t
-t
-t
tin
App
cyc
cyc
op
1
1
f
4
CLK_IN to any output
CLK_IN to any output
100MHz < f < 170MHz
f=66MHz
See figure 8
CONDITIONS
CONDITION
6
L
L
= 120 , C
= 120 , C
L
L
MIN
=15pF (unless otherwise stated)
=15pF (unless otherwise
33
60
40
wH
MIN
-150
550
49
1
/t
c
, were
MAX
233
170
100
60
TYP
5.5
5.5
50
72
75
0
UNITS
MHz
MHz
MAX
µs
%
150
100
950
51
65
75
4
ICS93716
UNITS
v/ns
ns
ns
ps
ps
ps
ps
ps
%