SI5315A-C-GMR Silicon Laboratories Inc, SI5315A-C-GMR Datasheet - Page 18

• Manufacturer Part Number: SI5315A-C-GMR
• Description: IC CLK MULT 8KHZ-644.53MHZ 36QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5315A-C-GMR

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 36-VQFN
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5315
3.2.3. Jitter Tolerance
Jitter tolerance is defined as the maximum peak-to-peak sinusoidal jitter that can be present on the incoming clock
before the DSPLL loses lock. The tolerance is a function of the jitter frequency, because tolerance improves for
lower input jitter frequency.
The jitter tolerance of the DSPLL is a function of the loop bandwidth setting. Figure 8 shows the general shape of
the jitter tolerance curve versus input jitter frequency. For jitter frequencies above the loop bandwidth, the tolerance
is a constant value A
lower input jitter frequencies.
The equation for the high frequency jitter tolerance can be expressed as a function of the PLL loop bandwidth
(i.e., BW):
For example, the jitter tolerance when f
3.2.4. Jitter Attenuation Performance
The Internal VCO uses the reference clock on the XA/XB pins as its reference for jitter attenuation. The XA/XB pins
support either a crystal input or an input buffer single-ended or differential clock input, such that an external
oscillator can become the reference source. In either case, the device accepts a wide margin in absolute frequency
of the reference input. (See 4.5. "Holdover Mode" on page 35.) In holdover, the Si5315's output clock stability
matches the reference supplied on the XA/XB pins. The external crystal or reference clock must be selected based
on the stability requirements of the application if holdover is a key requirement.
However, care must be exercised in certain areas for optimum performance. For examples of connections to the
XA/XB pins, refer to 6. "Crystal/Reference Clock Input" on page 41.
18
Amplitude
Input
Jitter
A
j0
j0
. Beginning at the PLL bandwidth, the tolerance increases at a rate of 20 dB/decade for
BW/100 BW/10
Figure 8. Jitter Tolerance Mask/Template
in
= 19.44 MHz, f
–20 dB/dec.
A
j0
=
A
j0
5000
------------ -
113
=
Excessive Input Jitter Range
Rev. 0.26
5000
------------ - ns pk-pk
BW
=
out
BW
44.24 ns pk-pk
= 161.13 MHz and the loop bandwidth (BW) is 113 Hz:
f
Jitter In