SI5315A-C-GMR Silicon Laboratories Inc, SI5315A-C-GMR Datasheet - Page 45

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SI5315A-C-GMR

Manufacturer Part Number
SI5315A-C-GMR
Description
IC CLK MULT 8KHZ-644.53MHZ 36QFN
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI5315A-C-GMR

Input
*
Output
*
Frequency - Max
*
Voltage - Supply
*
Operating Temperature
*
Mounting Type
Surface Mount
Package / Case
36-VQFN
Frequency-max
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8. Typical Phase Noise Plots
The following is a typical phase noise plot. The clock input source was a Rohde and Schwarz model SML03 RF
Generator. The spectrum analyzer was either an Agilent model E5052B, model E4400A or model JS-500. The
Si5315 operates at 3.3 V with an ac coupled differential PECL output and an ac coupled differential sine wave input
from the RF generator at 0 dBm. Note that, as with any PLL, the output jitter that is below the loop BW is caused by
the jitter at the input clock, not the Si5315. Except as noted, loop BWs of 60 to 240 Hz were in use.
8.1. Example: 10G LAN SyncE
Jitter Integration Filter Band
IEEE802.3 (1.875 to 20 MHz)
SONET OC-192 (20 kHz to 80 MHz)
SONET OC-192 (4 to 80 MHz)
SONET OC-192 (50 kHz to 80 MHz)
SONET OC-48 (12 kHz to 20 MHz)
SONET OC-3 (12 kHz to 5 MHz)
BroadBand (800 Hz to 80 MHz)
‐100
‐120
‐140
‐160
‐180
‐20
‐40
‐60
‐80
0
100
1,000
10,000
Fout=156.25 MHz
Fin=19.44 MHz
Si5315 Typical Phase Noise 
BW=167 Hz
100,000
232
483
302
467
470
422
511
Rev. 0.26
1,000,000
Fin=19.44 MHz
Fout=125 MHz
BW=111 Hz
240
575
303
564
565
524
584
Frequency Plan
RMS Jitter (fs)
10,000,000
Fout=156.25 MHz
Fin=25 MHz
BW=111 Hz
251
525
300
510
517
471
533
100,000,000
Fout=125 MHz
Si5315
Fin=19.44 MHz;
Fout=125 MHz;
BW=111 Hz
Fin=19.44 MHz
Fout=156.25 MHz
BW=167 Hz
Fin=25 MHz
Fout=125 MHz
BW=111 Hz
Fin=25 MHz
Fout=156.25 MHz
BW=111 Hz
Fin=25 MHz
BW=111 Hz
240
550
294
537
541
503
557
45

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