SI5319C-C-GM Silicon Laboratories Inc, SI5319C-C-GM Datasheet

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REQUENCY RECISION Features Generates any frequency from 2 kHz to 945 MHz and  select frequencies to 1.4 GHz from an input frequency of 2 kHz to 710 MHz Ultra-low jitter clock output with jitter generation ...

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Si5319 2 Rev. 1.0 ...

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T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Si5319 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Ambient Temperature T A Supply Voltage during V DD Normal Operation Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply ...

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Table 2. DC Characteristics (V = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol 1 Supply Current CKIN Input Pin Input Common Mode V ICM Voltage (Input Thresh- old Voltage) Input Resistance ...

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Si5319 Table 2. DC Characteristics (Continued 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Common Mode Output CKO VCM Voltage Differential Output CKO VD Voltage Common Mode Output CKO VCM Voltage Differential Output ...

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Table 2. DC Characteristics (Continued 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol 2-Level LVCMOS Input Pins Input Voltage Low V IL Input Voltage High 3-Level Input Pins Input Voltage ...

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Si5319 Table 2. DC Characteristics (Continued 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Output Voltage High V OH Output Voltage High Disabled Leakage I OZ Current Notes: Current draw is independent of ...

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Table 3. Microprocessor Control (Continued 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Low Time, SCLK t lsc High Time, SCLK t hsc Delay Time, SCLK Fall SDO Active Delay ...

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Si5319 Table 4. AC Specifications (Continued 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Input Duty Cycle CKN DC (Minimum Pulse Width) Input Capacitance CKN CIN Input Rise/Fall Time CKN TRF CKOUT Output ...

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Table 4. AC Specifications (Continued 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol LVCMOS Output Pins Rise/Fall Times t RF LOSn Trigger Window LOS TRIG Time to Clear LOL t CLRLOL after LOS ...

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Si5319 Table 5. Jitter Generation Parameter Symbol Measurement Jitter Gen J 0.02–80 MHz GEN OC-192 4–80 MHz 0.05–80 MHz Jitter Gen J 0.12–20 MHz GEN OC-48 *Note: Test conditions: 1. fIN = fOUT = 622.08 MHz 2. Clock input: LVPECL ...

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Table 7. Absolute Maximum Limits Parameter DC Supply Voltage LVCMOS Input Voltage CKINn Voltage Level Limits XA/XB Voltage Level Limits Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 k); All pins except CKIN+/CKIN– ESD MM Tolerance; ...

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Si5319 2. Typical Phase Noise Plots The following typical phase noise plot was taken using a Rohde and Schwarz SML03 RF Generator as the clock input source to the Si5326. The Agilent model E5052B was used for the phase noise ...

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S yste errite 3   – 8 ...

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Si5319 3. Functional Description The Si5319 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from ...

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Register Map All register bits that are not defined in this map should always be written with the specified Reset Values. The writing to these bits of values other than the specified Reset Values may result in undefined device ...

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Si5319 Register D7 D6 128 129 130 131 132 134 135 PARTNUM_RO[3:0] 136 RST_REG ICAL 138 139 185 PARTNUM_RO[11:4] LOS_EN [0:0] NVM_REVID[7:0] Rev. 1 CK_ACTV_ REG LOS_INT LOSX_INT LOL_INT LOS_FLG LOSX_FLG LOL_FLG REVID_RO[3:0] ...

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Register 0. Bit D7 D6 FREE_ Name RUN R R/W Type Reset value = 0001 0100 Bit Name 7 Reserved Reserved. 6 FREE_RUN Free Run. Internal to the device, route XA/XB to CKIN2. This allows the device to lock to ...

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Si5319 Register 2. Bit D7 D6 BWSEL_REG [3:0] Name R/W Type Reset value = 0100 0010 Bit Name 7:4 BWSEL_REG BWSEL_REG. [3:0] Selects nominal f3dB bandwidth for PLL. See the DSPLLsim for settings. After BWSEL_REG is written with a new ...

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Register 5. Bit D7 D6 ICMOS [1:0] Name R/W Type Reset value = 1110 1101 Bit Name 7:6 ICMOS [1:0] ICMOS [1:0]. When the output buffer is set to CMOS mode, these bits determine the output buffer drive strength. The ...

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Si5319 Register 8. Bit D7 D6 Reserved Name R Type Reset value = 0000 0000 Bit Name 7:6 Reserved Reserved. 5:4 HLOG [1:0]. 00: Normal operation. 01: Holds CKOUT output at static logic 0. Entrance and exit from this state ...

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Register 11. Bit D7 D6 Name Type Reset value = 0100 0000 Bit Name 7:1 Reserved Reserved. 0 PD_CK PD_CK. This bit controls the powerdown of the CKIN input buffer. 0: CKIN enabled. 1: CKIN disabled. Register 19. Bit D7 ...

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Si5319 Register 20. Bit D7 D6 Name Type Reset value = 0011 1110 Bit Name 7:2 Reserved Reserved. 1 LOL_PIN LOL_PIN. The LOL_INT status bit can be reflected on the LOL output pin. 0: LOL output pin tristated 1: LOL_INT ...

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Register 23. Bit D7 D6 Name Type Reset value = 0001 1111 Bit Name 7:2 Reserved Reserved. 1 LOS_MSK LOS_MSK. Determines if a LOS on CKIN (LOS_FLG) is used in the generation of an interrupt. Writes to this register do ...

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Si5319 Register 25. Bit D7 D6 N1_HS [2:0] Name R/W Type Reset value = 0010 0000 Bit Name 7:5 N1_HS [2:0] N1_HS [2:0]. Sets value for N1 high speed divider which drives NC1_LS low-speed divider. 000: N1= 4 001: N1= ...

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Register 32. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 NC1_LS NC1_LS [15:8]. [15:8] Sets value for NC1_LS, which drives CKOUT output. The value of the register must be either odd or zero. 00000000000000000000 = ...

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Si5319 Register 40. Bit D7 D6 N2_HS [2:0] Name R/W Type Reset value = 1100 0000 Bit Name 7:5 N2_HS [2:0] N2_HS [2:0]. Sets value for N2 high speed divider which drives N2_LS low-speed divider. 000: 4 001: 5 010: ...

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Register 41. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 N2_LS [15:8] N2_LS [15:8]. Sets value for N2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 ...

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Si5319 Register 43. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:3 Reserved Reserved. 2:0 N31 [18:16] N31 [18:16]. Sets value for input divider for CKIN. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... ...

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Register 45. Bit D7 D6 Name Type Reset value = 0000 1001 Bit Name 7:0 N31_[7:0 N31_[7:0]. Sets value for input divider for CKIN. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 Valid divider values=[1, ...

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Si5319 Register 47. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 N32_[15:8] N32_[15:8]. Sets value for input divider for the XO clock in free-run mode. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... ...

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Register 128. Bit D7 D6 Name Type Reset value = 0010 0000 Bit Name 7:1 Reserved Reserved. 0 CK_ACTV_ CK_ACTV_REG. REG Indicates if CKIN is currently the active clock for the PLL input. 0: CKIN is not the active input ...

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Si5319 Register 130. Bit D7 D6 Name Type Reset value = 0000 0001 Bit Name 7:3 Reserved Reserved. 0 LOL_INT PLL Loss of Lock Status. 0: PLL locked. 1: PLL unlocked. Register 131. Bit D7 D6 Name Type Reset value ...

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Register 132. Bit D7 D6 Name Type Reset value = 0000 0010 Bit Name 7:2, 0 Reserved Reserved. 1 LOL_FLG PLL Loss of Lock Flag. 0: PLL locked 1: Held version of LOL_INT. Generates active output interrupt if output interrupt ...

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Si5319 Register 135. Bit D7 D6 PARTNUM_RO [3:0] Name R Type Reset value = 1010 0010 Bit Name 7:4 PARTNUM_ Device 2). RO [11:0] 0000 0001 + 0011: Si5319 3:0 REVID_RO Indicates Revision Number of Device. [3:0] ...

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Register 136. Bit D7 D6 RST_REG ICAL Name R/W R/W Type Reset value = 0000 0000 Bit Name 7 RST_REG Internal Reset (Same as Pin Reset). Note: The I2C (or SPI) port may not be accessed until 10 ms after ...

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Si5319 Register 138. Bit D7 D6 Name Type Reset value = 0000 1111 Bit Name 7:3 Reserved Reserved. 0 LOS_EN [1:0] Enable CKIN LOS Monitoring on the Specified Input (1 of 2). Note: LOS_EN is split between two registers. 00: ...

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Register 185. Bit D7 D6 Name Type Reset value = 0001 0011 Bit Name 7:0 NVM_REVID [7:0] NVM_REVID. Table 8. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table CKOUT_ALWAYS_ON Table 9 lists all of the register locations that should ...

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Si5319 5. Pin Descriptions: Si5319 INT_CB Pin # Pin Name I/O Signal Level 1 I LVCMOS RST — — 12–14, 30, 33–35 3 INT_CB O LVCMOS 5, 10 Supply Note: Internal ...

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Pin # Pin Name I/O Signal Level Analog Supply GND GND 19,20 11 RATE0 I 3-Level 15 RATE1 16 CKIN+ I Multi 17 CKIN– 18 LOL O LVCMOS LVCMOS 22 ...

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Si5319 Pin # Pin Name I/O Signal Level LVCMOS A2_SS I LVCMOS 27 SDI I LVCMOS 29 CKOUT– O Multi 28 CKOUT+ 36 CMODE I LVCMOS GND GND GND Supply PAD Note: Internal register ...

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... Number Frequency Range Si5319A-C-GM 2 kHz–945 MHz 970–1134 MHz 1.213–1.417 GHz Si5319B-C-GM 2 kHz–808 MHz Si5319C-C-GM 2 kHz–346 MHz Note: Add the end of the device part number to denote tape and reel ordering options. ROHS6, Package Pb-Free 36-Lead QFN Yes ...

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Si5319 7. Package Outline: 36-Pin QFN Figure 6 illustrates the package details for the Si5319. Table 10 lists the values for the dimensions shown in the illustration.   Figure 6. 36-Pin Quad Flat No-lead (QFN) Symbol Millimeters Min A 0.80 ...

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Recommended PCB Layout Figure 8. Ground Pad Recommended Layout Figure 7. PCB Land Pattern Diagram Rev. 1.0 Si5319 45 ...

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Si5319 Table 11. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI ...

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Si5319 Device Top Mark Laser Mark Method: 0.80 mm Font Size: Right-Justified Si5319 Line 1 Marking: C-GM Line 2 Marking: YYWWRF Line 3 Marking: Pin 1 Identifier Line 4 Marking: XXXX Customer Part Number Q = Speed Code: A, ...

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Si5319 OCUMENT HANGE IST Revision 0.1 to Revision 0.2 Changed 1.8 V operating range to ±5%.  Updated Table 1 on page 4.  Updated Table 2 on page 5.  Added table under Figure 3 on ...

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N : OTES Rev. 1.0 Si5319 49 ...

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