SI5366-C-GQ Silicon Laboratories Inc, SI5366-C-GQ Datasheet
SI5366-C-GQ
Specifications of SI5366-C-GQ
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SI5366-C-GQ Summary of contents
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... VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8 or 2.5 V supply, the Si5366 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Applications ...
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... Si5366 Table 1. Performance Specifications (V = 1.8 ±5% or 2.5 V ±10 – º Parameter Symbol Temperature Range T A Supply Voltage V DD Supply Current I DD Input Clock Frequency CK F (CKIN1, CKIN2, CKIN3, CKIN4) Input Clock Frequency CK F (CKIN3, CKIN4 used as FSYNC inputs) Output Clock Frequency ...
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... MHz offset Phase Noise @ 100 kHz Offset Max spur @ > < 100 MHz) Still Air www.silabs.com/timing Symbol DIG T JCT T STG Preliminary Rev. 0.3 Si5366 Min Typ Max Unit 45 — — 0.3 TBD ps rms — 0.3 TBD ps rms — ...
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... Si5366 622 MHz In, 622 MHz Out BW=877 kHz -50 -70 -90 -110 -130 -150 -170 1000 10000 OC-48, 12 kHz to 20 MHz OC-192, 20 kHz to 80 MHz OC-192, 4 MHz to 80 MHz OC-192, 50 kHz to 80 MHz Broadband, 800 MHz 4 100000 1000000 Offset Frequency (Hz) Figure 1. Typical Phase Noise Plot ...
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... FS_ALIGN Control Reset RST Notes: 1. Assumes differential LVPECL termination (3 clock inputs. 2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD). 3. Assumes manual input clock selection. Figure 2. Si5366 Typical Application Circuit C 10 Option 1: Option 2: Ext. Ext. 1 µF Refclk– ...
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... SONET, Ethernet, and Fibre Channel rates. In addition to providing clock multiplication in SONET and datacom applications, the Si5366 supports SONET- to-datacom frequency translations. Silicon Laboratories offers a PC-based software utility, DSPLLsim, that can be used to look up valid Si5366 frequency translations. This utility can be downloaded http://www ...
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... Table 3. Si5366 Pin Descriptions Signal Level No Connect. These pins must be left unconnected for normal operation. LVCMOS External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state and forces the device registers to their default value. Clock outputs are dis- abled during reset ...
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... Si5366 Table 3. Si5366 Pin Descriptions (Continued) Pin # Pin Name I/O 4 FRQTBL 15, 27 62, 63, 76, 79, 81, 84, 86, 89, 91, 94, 96, 99, 100 7, 8, 14, 18, GND GND 19, 26, 28, 31, 33, 36, 38, 41, 43, 46, 64 C1B O 10 C2B O 11 C3B O 8 Signal Level 3-Level Frequency Table Select. This pin selects SONET/SDH, datacom, or SONET/SDH to datacom frequency translation table ...
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... Table 3. Si5366 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 12 ALRMOUT O LVCMOS 13 CS0_C3A I/O LVCMO 57 CS1_C4A ANALOG FS_SW I LVCMOS 21 FS_ALIGN I LVCMOS Description Alarm Output Indicator. This pin is an active high alarm output associated with CKIN4 or the frame sync alignment alarm. ...
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... Si5366 Table 3. Si5366 Pin Descriptions (Continued) Pin # Pin Name I/O 22 AUTOSEL I 29 CKIN4 CKIN4– 32 RATE0 I 42 RATE1 34 CKIN2 CKIN2– 37 DBL2_BY I 39 CKIN3 CKIN3– 44 CKIN1 CKIN1– 49 LOL O 10 Signal Level 3-Level Manual/Automatic Clock Selection. Three level input that selects the method of input clock selec- tion to be used ...
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... Table 3. Si5366 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 50 DBL_FS I 3-Level 51 CK_CONF I LVCMOS 54 DEC I LVCMOS 55 INC I LVCMOS Description FS_OUT Disable. This pin performs the following functions Normal operation. Output path is active and signal format is determined by SFOUT inputs CMOS signal format. Overrides SFOUT signal format to allow FS_OUT to operate in CMOS format while the clock out- puts operate in a differential output format ...
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... Si5366 Table 3. Si5366 Pin Descriptions (Continued) Pin # Pin Name I/O 56 FOS_CTL I 58 C1A O 59 C2A O 60 BWSEL0 I 61 BWSEL1 66 DIV34_0 I 67 DIV34_1 68 FRQSEL0 I 69 FRQSEL1 70 FRQSEL2 71 FRQSEL3 12 Signal Level 3-Level Frequency Offset Control. This pin enables or disables use of the CKIN2 FOS reference as an input to the clock selection state machine ...
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... Table 3. Si5366 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 77 CKOUT3 CKOUT3– 80 SFOUT1 I 3-Level 95 SFOUT0 82 CKOUT1– CKOUT1+ 85 DBL34 I LVCMOS 87 FS_OUT– FS_OUT+ MULTI Clock Output 3. Differential output clock with a frequency specified by FRQSEL and FRQTBL settings. Output is differential for LVPECL, LVDS, and CML compatible modes ...
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... Si5366 Table 3. Si5366 Pin Descriptions (Continued) Pin # Pin Name I/O 92 CKOUT2 CKOUT2– 97 CKOUT4– CKOUT4+ GND PAD GND PAD GND 14 Signal Level MULTI Clock Output 2. Differential output clock with a frequency specified by FRQSEL and FRQTBL. Output signal format is selected by SFOUT pins. ...
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... Ordering Guide Ordering Part Number Si5366-C-GQ 100-Pin TQFP Package ROHS6, Pb-Free Yes Preliminary Rev. 0.3 Si5366 Temperature Range – °C 15 ...
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... Si5366 4. Package Outline: 100-Pin TQFP Figure 3 illustrates the package details for the Si5366. Table 4 lists the values for the dimensions shown in the illustration. Figure 3. 100-Pin Thin Quad Flat Package (TQFP) Table 4. Dimension Min Nom A — A1 0.05 A2 0.95 1.00 b 0.17 0. ...
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... Recommended PCB Layout Figure 4. PCB Land Pattern Diagram Preliminary Rev. 0.3 Si5366 17 ...
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... Si5366 Table 5. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0 ...
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... Updated “2. Pin Descriptions: Si5366”. Updated "3. Ordering Guide" on page 15. Added “5. Recommended PCB Layout”. Revision 0.2 to Revision 0.3 Changed 1.8 V operating range to ±5%. Clarified "2. Pin Descriptions: Si5366" on page 7. Updated "4. Package Outline: 100-Pin TQFP" on page 16. Preliminary Rev. 0.3 Si5366 ...
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... Si5366 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...