SI5366-C-GQ Silicon Laboratories Inc, SI5366-C-GQ Datasheet - Page 6

• Manufacturer Part Number: SI5366-C-GQ
• Description: IC CLOCK MULTIPLIER PREC 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5366-C-GQ

• Package / Case: 100-TQFP, 100-VQFP
• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Frequency-max: *
• Number Of Circuits: 1
• Maximum Input Frequency: 707.35 MHz
• Minimum Input Frequency: 0.008 MHz
• Output Frequency Range: 0.008 MHz to 1049.76 MHz
• Supply Voltage (max): 2.75 V
• Supply Voltage (min): 1.71 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Si5366
1. Functional Description
The Si5366 is a jitter-attenuating precision clock
multiplier for high-speed communication systems,
including SONET OC-48/OC-192, Ethernet, and Fibre
Channel. The Si5366 accepts four clock inputs ranging
from 8 kHz to 707 MHz and generates five frequency-
multiplied clock outputs ranging from 8 kHz to
1050 MHz. By default the four clock inputs are at the
same frequency and the five clock outputs are at the
same frequency. Two of the output clocks can be
divided down further to generate an integer sub-multiple
frequency. Optionally, the fifth clock output can be
configured
synchronization output that is phase aligned with one of
the high-speed output clocks. The input clock frequency
and clock multiplication ratio are selectable from a table
of popular SONET, Ethernet, and Fibre Channel rates.
In addition to providing clock multiplication in SONET
and datacom applications, the Si5366 supports SONET-
to-datacom frequency translations. Silicon Laboratories
offers a PC-based software utility, DSPLLsim, that can
be used to look up valid Si5366 frequency translations.
This
http://www.silabs.com/timing
The Si5366 is based on Silicon Laboratories' 3rd-
generation DSPLL
rate frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need
for external VCXO and loop filter components. The
Si5366 PLL loop bandwidth is selectable via the
BWSEL[1:0] pins and supports a range from 60 Hz to
8.4 kHz. The DSPLLsim software utility can be used to
calculate valid loop bandwidth settings for a given input
clock frequency/clock multiplication ratio.
The Si5366 supports hitless switching between input
clocks in compliance with GR-253-CORE and GR-1244-
CORE that greatly minimizes the propagation of phase
transients to the clock outputs during an input clock
transition (<200 ps typ). Manual and automatic revertive
and non-revertive input clock switching options are
available via the AUTOSEL input pin. The Si5366
monitors the four input clocks for loss-of-signal and
provides a LOS alarm when it detects missing pulses on
any of the four input clocks. The device monitors the
lock status of the PLL. The lock detect algorithm works
by continuously monitoring the phase of the input clock
in relation to the phase of the feedback clock. If a
potential phase cycle slip is detected, the LOL output is
set high. The Si5366 monitors the frequency of CKIN1,
CKIN3, and CKIN4 with respect to a reference
frequency applied to CKIN2, and generates a frequency
offset alarm (FOS) if the threshold is exceeded. This
FOS feature is available for SONET applications in
which both the monitored frequency on CKIN1, CKIN3,
and CKIN4 and the reference frequency are integer
multiples of 19.44 MHz. Both Stratum 3/3E and SONET
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Minimum Clock (SMC) FOS thresholds are supported.
The Si5366 provides a digital hold capability that allows
the device to continue generation of a stable output
clock when the selected input reference is lost. During
digital hold, the DSPLL is locked to an input frequency
that existed a fixed amount of time before the error
event occurred, eliminating the effects of phase and
frequency transients that may occur immediately
preceding digital hold.
The Si5366 has five differential clock outputs. The
signal format of the clock outputs is selectable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, unused clock outputs can be powered down to
minimize power consumption. The phase difference
between the selected input clock and the output clocks
is adjustable in 200 ps increments for system skew
control. For system-level debugging, a bypass mode is
available which drives the output clock directly from the
input clock, bypassing the internal DSPLL. The device is
powered by a single 1.8 or 2.5 V supply.
1.1. External Reference
An
114.285 MHz 3rd overtone crystal is used as part of a
fixed-frequency oscillator within the DSPLL. This
external reference is required for the device to perform
jitter attenuation. Silicon Laboratories recommends
using a high-quality crystal. Specific recommendations
may be found in the Family Reference Manual. An
external 38.88 MHz clock from a high quality OCXO or
TCXO can also be used as a reference for the device.
In digital hold, the DSPLL remains locked to this
external reference. Any changes in the frequency of this
reference when the DSPLL is in digital hold, will be
tracked by the output of the device. Note that crystals
can have temperature sensitivities.
1.2. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for detailed
information about the Si5366. Additional design support
is available from Silicon Laboratories through your
distributor.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
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