SI5368C-C-GQ Silicon Laboratories Inc, SI5368C-C-GQ Datasheet - Page 33

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SI5368C-C-GQ

Manufacturer Part Number
SI5368C-C-GQ
Description
IC CLK MULTIPLIER ATTEN 100TQFP
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI5368C-C-GQ

Package / Case
100-TQFP, 100-VQFP
Input
*
Output
*
Frequency - Max
*
Voltage - Supply
*
Operating Temperature
*
Mounting Type
Surface Mount
Frequency-max
*
Number Of Circuits
1
Maximum Input Frequency
710 MHz
Minimum Input Frequency
0.002 MHz
Output Frequency Range
0.002 MHz to 346 MHz
Supply Voltage (max)
2.75 V
Supply Voltage (min)
1.71 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
1.8 V, 2.5 V
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI5368C-C-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
SI5368C-C-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Reset value = 1000 0000
Reset value = 0000 0000
Register 17.
Register 18.
Name
Name
Type
Type
Bit
Bit
6:0
7:0
Bit
Bit
7
FLAT_VAILD FLAT_VAILD.
FLAT [14:0]
FLAT [7:0]
FLAT_
VALID
R/W
Name
Name
D7
D7
Before writing a new FLAT[14:0] value, this bit must be set to zero, which causes the
existing FLAT[14:0] value to be held internally for use while the new value is being writ-
ten. Once the new FLAT[14:0] value is completely written, set FLAT_VALID = 1 to enable
its use.
0: Memorize existing FLAT[14:0] value and ignore intermediate register values during
write of new FLAT[14:0] value.
1: Use FLAT[14:0] value directly from registers.
FLAT [14:0].
Fine resolution control for overall device latency from input clocks to output clocks.
Positive values increase the skew. See DSPLLsim for details.
FLAT [7:0].
See Register 17.
D6
D6
D5
D5
Preliminary Rev. 0.41
D4
D4
FLAT [7:0]
R/W
FLAT [14:8]
Function
Function
R/W
D3
D3
D2
D2
D1
D1
Si5368
D0
D0
33

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