SI5368A-C-GQR Silicon Laboratories Inc, SI5368A-C-GQR Datasheet - Page 15

• Manufacturer Part Number: SI5368A-C-GQR
• Description: IC CLK MULTIPLIER ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5368A-C-GQR

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
GND PAD
Pin #
71
77
78
82
83
87
88
90
92
93
97
98
CKOUT3+
CKOUT3–
CKOUT1–
CKOUT1+
CKOUT2+
CKOUT2–
CKOUT4–
CKOUT4+
Pin Name
FS_OUT–
FS_OUT+
GND PAD
CMODE
SDI
GND
I/O
Table 3. Si5368 Pin Descriptions (Continued)
O
O
O
O
O
I
I
Signal Level
LVCMOS
LVCMOS
Supply
MULTI
MULTI
MULTI
MULTI
MULTI
Preliminary Rev. 0.41
Serial Data In.
In SPI microprocessor control mode (CMODE = 1), this pin
functions as the serial data input.
In I
ignored.
This pin has a weak pull-down.
Clock Output 3.
Differential clock output. Output signal format is selected by
SFOUT3_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
Clock Output 1.
Differential clock output. Output signal format is selected by
SFOUT1_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
Frame Sync Output.
Differential frame sync output or fifth high-speed clock output.
Output signal format is selected by SFOUT_FSYNC_REG reg-
ister bits. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs. Duty cycle and active
polarity are controlled by FSYNC_PW and FSYNC_POL bits,
respectively. Detailed operations and timing characteristics for
these pins may be found in the Any-Rate Precision Clock Fam-
ily Reference Manual.
Control Mode.
Selects I
0 = I
1 = SPI Control Mode.
This pin must be tied high or low.
Clock Output 2.
Differential clock output. Output signal format is selected by
SFOUT2_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
Clock Output 4.
Differential clock output. Output signal format is selected by
SFOUT4_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
2
C microprocessor control mode (CMODE = 0), this pin is
2
C Control Mode.
2
C or SPI control mode for the device.
Description
Si5368
15