SI5368A-C-GQR Silicon Laboratories Inc, SI5368A-C-GQR Datasheet - Page 31

• Manufacturer Part Number: SI5368A-C-GQR
• Description: IC CLK MULTIPLIER ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5368A-C-GQR

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset value = 0000 0001
Reset value = 0000 0000
Register 13.
Register 14.
Name
Name
Type
Type
Bit
Bit
1:0
7:0
7:0
Bit
Bit
2
SKEW [16:0]
SKEW [15:8]
FSYNC_PW
FSYNC_
FSYNC_
FSYNC_
PW [9:0]
Name
Name
D7
D7
[7:0]
FSYNC_SKEW [16:0].
Phase skew control for FSYNCOUT. The resolution of the skew control is 1/fCKOUT2.
Entered values should be less than the FSYNCOUT period.
0 0000 0000 0000 0000=Zero phase skew.
0 0000 0000 0000 0001=Delay of 1 period of CLKOUT_2.
1 0010 1111 1011 1111=Delay of 77,759 periods of CKOUT2. If CKOUT2=622.08 MHz
and FSYNCOUT=8 kHz, this delay equals 125 ms - 1/fCKOUT2 and is the maximum
value that should be entered.
1 1111 1111 1111 1111=Delay of 131,071 periods of CKOUT2.
FSYNC_PW [9:0].
These bits control the pulse width of the FSYNCOUT signal. The resolution of the pulse
width control is 1/fCKOUT2.
0000000000=50% duty cycle.
0000000001=1 period of CKOUT2.
0000000010=2 periods of CKOUT2.
1111111111=1023 periods of CKOUT2.
FSYNC_PW [7:0].
See Register 12.
FSYNC_SKEW [15:8].
See Register 12.
D6
D6
D5
D5
Preliminary Rev. 0.41
FSYNC_SKEW [15:8]
FSYNC_PW [7:0]
D4
D4
R/W
R/W
Function
Function
D3
D3
D2
D2
D1
D1
Si5368
D0
D0
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