MC100EP196BFAR2G ON Semiconductor, MC100EP196BFAR2G Datasheet
MC100EP196BFAR2G
Specifications of MC100EP196BFAR2G
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MC100EP196BFAR2G Summary of contents
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MC100EP196B 3.3 V ECL Programmable Delay Chip With FTUNE Descriptions The MC100EP196B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture ...
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D10 MC100EP196B Warning: All V and V pins must be externally ...
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Table 1. PIN DESCRIPTION Pin Name I/O 23, 25, 26, 27, D[0:9] LVCMOS, LVTTL, 29, 30, 31, 32, ECL Input D[10] LVCMOS, LVTTL, ECL Input 4 IN LVPECL, LVDS 5 IN LVPECL, LVDS 6 V − BB ...
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Table 2. CONTROL PIN Pin State EN LOW (Note 3) HIGH LEN LOW (Note 3) HIGH SETMIN LOW (Note 3) HIGH SETMAX LOW (Note 3) HIGH D10 LOW (Note 3) HIGH 3. Internal pulldown resistor will provide a logic LOW ...
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Figure 3. Logic Diagram http://onsemi.com 5 ...
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Table 6. THEORETICAL DELAY VALUES D(9:0) Value XXXXXXXXXX 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 1111111111 XXXXXXXXXX *Fixed minimum delay not included. Table 7. TYPICAL FTUNE DELAY PIN Input Range V −V ...
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Table 8. MAXIMUM RATINGS Symbol Parameter V Positive Mode Power Supply CC V Negative Mode Power Supply EE V Positive Mode ...
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Table 9. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Negative Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended) IL ...
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Table 10. 100EP DC CHARACTERISTICS, NECL Symbol Characteristic I Negative Power Supply Current EE (Note 11) V Output HIGH Voltage (Note 12 Output LOW Voltage (Note 12 Input HIGH Voltage (Single−Ended Input LOW Voltage ...
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Table 11. AC CHARACTERISTICS V Symbol Characteristic f Maximum Frequency max V Output Voltage Amplitude outpp t Propagation Delay PLH D(0−10 SETMIN PHL D(0−10) = 1023, SETMAX D(0−10) ...
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Using the FTUNE Analog Input The analog FTUNE pin on the EP196 device is intended to add more delay in a tunable gate to enhance the 10 ps resolution capabilities of the fully digital EP196. The level of resolution obtained ...
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Need if Chip #3 is used D10 EP196B IN INPUT IN CHIP # A11 A10 ...
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An expansion of the latch section of the block diagram is pictured in Figure 8. Use of this diagram will simplify the explanation of how the cascade circuitry works. When D10 of chip #1 in Figure 7 is LOW this ...
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Table 12. Delay Value of Two EP196B Cascaded VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2 INPUT FOR CHIP #1 D10 ...
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Multi−Channel Deskewing The most practical application for EP196B is in multiple channel delay matching. Slight differences in impedance and cable length can create large timing skews within a high−speed system. To deskew multiple signal channels, each channel can Digital Data ...
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... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100EP196BFA MC100EP196BFAG MC100EP196BFAR2 MC100EP196BFAR2G MC100EP196BMNG MC100EP196BMNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes ...
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−T− DETAIL −Z− −AB− −AC− SEATING PLANE 0.10 (0.004) AC PACKAGE DIMENSIONS 32 LEAD LQFP CASE 873A−02 ISSUE C 4X 0.20 (0.008) AB T-U Z −U− ...
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... X 0.28 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...