IC PROGRAM DELAY 3.3V ECL 32-QFN

MC100EP196BMNR4G

Manufacturer Part NumberMC100EP196BMNR4G
DescriptionIC PROGRAM DELAY 3.3V ECL 32-QFN
ManufacturerON Semiconductor
Series100EP
TypeProgrammable Delay Chip
MC100EP196BMNR4G datasheet
 


Specifications of MC100EP196BMNR4G

InputECL, LVCMOS, LVTTLOutputECL
Frequency - Max1.2GHzVoltage - Supply3 V ~ 3.6 V
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case32-TFQFN Exposed PadFrequency-max1.2GHz
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther namesMC100EP196BMNR4GOS
MC100EP196BMNR4GOS
MC100EP196BMNR4GOSTR
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MC100EP196B
3.3 V ECL Programmable
Delay Chip With FTUNE
Descriptions
The MC100EP196B is a Programmable Delay Chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides variable
delay of a differential NECL/PECL input transition. It has similar
architecture to the EP195 with the added feature of further tunability in
delay using the FTUNE pin. The FTUNE input takes an analog voltage
from V
to V
to fine tune the output delay from 0 to 60 ps.
CC
EE
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 3. The delay
increment of the EP196B has a digitally selectable resolution of about
10 ps and a net range of up to 10.4 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(Pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any subsequent
changes in D[10:0]. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
Table 6 and Figure 4.
The IN/IN inputs can accept LVPECL (SE or Diff), or LVDS level
signals. Because the MC100EP196B is designed using a chain of
multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin
D10 is provided for controlling Pins 14 and 15, CASCADE and
CASCADE, also latched by LEN, in cascading multiple PDCs for
increased programmable range. The cascade logic allows full control of
multiple PDCs. Switching devices from all “1” states on D[0:9] with
SETMAX LOW to all “0” states on D[0:9] with SETMAX HIGH will
increase the delay equivalent to “D0”, the minimum increment.
Select input pins D[10:0] may be threshold controlled by
combinations of interconnects between V
receiving LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
levels, leave V
and V
open. For ECL operation, short V
CF
EF
(Pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply
reference to V
and leave open V
pin. The 1.5 V reference voltage at
CF
EF
the V
pin can be accomplished by placing a 2.2 kW resistor between
CF
V
and V
for a 3.3 V power supply.
CF
EE
The V
pin, an internally generated voltage supply, is available to
BB
this device only. For single−ended input conditions, the unused
differential input is connected to V
BB
V
may also rebias AC coupled inputs. When used, decouple V
BB
via a 0.01 mF capacitor and limit current sourcing or sinking to
V
CC
0.5 mA. When not used, V
should be left open.
BB
The 100 Series contains temperature compensation.
Features
Maximum Input Clock Frequency >1.2 GHz Typical
Programmable Range: 0 ns to 10 ns
Delay Range: 2.2 ns to 12.4 ns
10 ps Increments
Linearity ±40 ps max
PECL Mode Operating Range:
V
= 3.0 V to 3.6 V with V
CC
© Semiconductor Components Industries, LLC, 2008
April, 2008 − Rev. 1
(pin 7) and V
(pin 8) for
EF
CF
and V
CF
EF
as a switching reference voltage.
and
BB
NECL Mode Operating Range:
IN/IN Inputs Accept LVPECL, LVNECL, LVDS Levels
A Logic High on the EN Pin Will Force Q to Logic Low
D[10:0] Can Select Either LVPECL, LVCMOS, or
LVTTL Input Levels
V
Output Reference Voltage
= 0 V
BB
EE
These are Pb−Free Devices
1
http://onsemi.com
MARKING
DIAGRAMS*
MC100
EP196B
AWLYYWWG
LQFP−32
FA SUFFIX
32
CASE 873A
1
1
MC100
1
32
EP196B
ALYWG
QFN32
MN SUFFIX
CASE 488AM
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
V
= 0 V with V
= −3.0 V to −3.6 V
CC
EE
Publication Order Number:
MC100EP196B/D

MC100EP196BMNR4G Summary of contents

  • Page 1

    MC100EP196B 3.3 V ECL Programmable Delay Chip With FTUNE Descriptions The MC100EP196B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture ...

  • Page 2

    D10 MC100EP196B Warning: All V and V pins must be externally ...

  • Page 3

    Table 1. PIN DESCRIPTION Pin Name I/O 23, 25, 26, 27, D[0:9] LVCMOS, LVTTL, 29, 30, 31, 32, ECL Input D[10] LVCMOS, LVTTL, ECL Input 4 IN LVPECL, LVDS 5 IN LVPECL, LVDS 6 V − BB ...

  • Page 4

    Table 2. CONTROL PIN Pin State EN LOW (Note 3) HIGH LEN LOW (Note 3) HIGH SETMIN LOW (Note 3) HIGH SETMAX LOW (Note 3) HIGH D10 LOW (Note 3) HIGH 3. Internal pulldown resistor will provide a logic LOW ...

  • Page 5

    Figure 3. Logic Diagram http://onsemi.com 5 ...

  • Page 6

    Table 6. THEORETICAL DELAY VALUES D(9:0) Value XXXXXXXXXX 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 1111111111 XXXXXXXXXX *Fixed minimum delay not included. Table 7. TYPICAL FTUNE DELAY PIN Input Range V −V ...

  • Page 7

    Table 8. MAXIMUM RATINGS Symbol Parameter V Positive Mode Power Supply CC V Negative Mode Power Supply EE V Positive Mode ...

  • Page 8

    Table 9. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Negative Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended) IL ...

  • Page 9

    Table 10. 100EP DC CHARACTERISTICS, NECL Symbol Characteristic I Negative Power Supply Current EE (Note 11) V Output HIGH Voltage (Note 12 Output LOW Voltage (Note 12 Input HIGH Voltage (Single−Ended Input LOW Voltage ...

  • Page 10

    Table 11. AC CHARACTERISTICS V Symbol Characteristic f Maximum Frequency max V Output Voltage Amplitude outpp t Propagation Delay PLH D(0−10 SETMIN PHL D(0−10) = 1023, SETMAX D(0−10) ...

  • Page 11

    Using the FTUNE Analog Input The analog FTUNE pin on the EP196 device is intended to add more delay in a tunable gate to enhance the 10 ps resolution capabilities of the fully digital EP196. The level of resolution obtained ...

  • Page 12

    Need if Chip #3 is used D10 EP196B IN INPUT IN CHIP # A11 A10 ...

  • Page 13

    An expansion of the latch section of the block diagram is pictured in Figure 8. Use of this diagram will simplify the explanation of how the cascade circuitry works. When D10 of chip #1 in Figure 7 is LOW this ...

  • Page 14

    Table 12. Delay Value of Two EP196B Cascaded VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2 INPUT FOR CHIP #1 D10 ...

  • Page 15

    Multi−Channel Deskewing The most practical application for EP196B is in multiple channel delay matching. Slight differences in impedance and cable length can create large timing skews within a high−speed system. To deskew multiple signal channels, each channel can Digital Data ...

  • Page 16

    ... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100EP196BFA MC100EP196BFAG MC100EP196BFAR2 MC100EP196BFAR2G MC100EP196BMNG MC100EP196BMNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D ...

  • Page 17

    −T− DETAIL −Z− −AB− −AC− SEATING PLANE 0.10 (0.004) AC PACKAGE DIMENSIONS 32 LEAD LQFP CASE 873A−02 ISSUE C 4X 0.20 (0.008) AB T-U Z −U− ...

  • Page 18

    ... X 0.28 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...