W134SH Cypress Semiconductor Corp, W134SH Datasheet

Page 1

... PCLKM Alignment SYNCLKN Test S0:1 Logic STOPB Cypress Semiconductor Corporation Document #: 38-07426 Rev. *B Direct Rambus™ Clock Generator Description The Cypress W134M/W134S provides the differential clock signals for a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus Channel clock to an ® ...

Page 2

Pin Definitions Pin Name No. Type REFCLK 2 I PCLKM 6 I SYNCLKN 7 I STOPB 11 I PWRDNB 12 I MULT 0:1 15 CLK, CLKB 20 S0 – VDDIR ...

Page 3

Key Specifications Supply Voltage: ...................................... V Operating Temperature: ................................... 0°C to +70°C Input Threshold: .................................................. 1.5V typical Maximum Input Voltage: ........................................ V Maximum Input Frequency: .....................................100 MHz Output Duty Cycle:...................................40/60% worst case Output Type: ...........................Rambus signaling level (RSL) DDLL System ...

Page 4

W133 W158 W159 W161 W167 CY2210 Figure 3 shows more details of the DDLL system architecture, including the DRCG output enable and bypass modes. Phase Detector Signals The DRCG Phase Detector receives two inputs from the core logic, PclkM (Pclk/M) ...

Page 5

Table 4. Bypass and Test Mode Selection Bypclk Mode S0 S1 (int.) Normal 0 0 Gnd Output Test (OE Bypass 1 0 PLLclk Test 1 1 Refclk Table 5 shows the logic for selecting the Power-down mode, using ...

Page 6

Timing Diagrams Power-down Exit and Entry PwrDnB Clk/ClkB Output Enable Control StopB Clk/ClkB Mult0 and/or Mult1 Clk/ClkB Table 8. State Transition Latency Specifications Transition From A Power-down C Power-down K Power-down ...

Page 7

Table 8. State Transition Latency Specifications (continued) Transition From E Clk Stop E Clk Stop F Normal L Test N Normal B,D Normal or Clk Stop Power-down t Figure 5 shows that the Clk Stop to Normal transition goes through ...

Page 8

Absolute Maximum Conditions Parameter V Max. voltage on V DD, ABS V Max. voltage on any pin with respect ground I, ABS External Component Values Parameter R Serial Resistor S R Parallel Resistor P C Edge Rate Filter Capacitor F ...

Page 9

Device Characteristics Parameter t Clock Cycle Time CYCLE t Cycle-to-Cycle Jitter at Clk/ClkB J Total Jitter over Clock Cycles 266-MHz Cycle-to-Cycle Jitter 266-MHz Total Jitter over Clock Cycles t Phase Aligner Phase ...

Page 10

... Layout Example VDDIR VDDIPD Ordering Information Ordering Code W134M/W134SH W134M/W134SHT W134M/W134SSQC W134M/W134SSQCT W134SH W134SHT Document #: 38-07426 Rev. *B +3.3V Supply FB 10 µF 0.005 µ Internal Power Supply Plane FB = Dale ILB1206 - 300 (300Ω @ 100 MHz VIA to GND plane layer All Bypass cap = 0.1 Ceramic XR7 24-pin QSOP (150 mils, SSOP) 24-pin QSOP (150 mils, SSOP) – ...

Page 11

... Document #: 38-07426 Rev. *B © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Page 12

Document History Page Document Title: W134M/W134S Direct Rambus™ Clock Generator Document Number: 38-07426 REV. ECN NO. Issue Date ** 115531 05/10/02 *A 122927 12/14/02 *B 131671 12/15/03 Document #: 38-07426 Rev. *B Orig. of Change DSG Change from Spec number: ...