W134SH Cypress Semiconductor Corp, W134SH Datasheet - Page 4

• Manufacturer Part Number: W134SH
• Description: IC CLK GEN DIR RAMBUS 3.3V24QSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Direct RAMbus Clock Generatorr

Specifications of W134SH

• Output: RSL
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-QSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Input: -
• Other names: 428-1475

Document #: 38-07426 Rev. *B
Figure 3 shows more details of the DDLL system architecture,
including the DRCG output enable and bypass modes.
Phase Detector Signals
The DRCG Phase Detector receives two inputs from the core
logic, PclkM (Pclk/M) and SynclkN (Synclk/N). The M and N
dividers in the core logic are chosen so that the frequencies of
PclkM and SynclkN are identical. The Phase Detector detects
the phase difference between the two input clocks, and drives
the DRCG Phase Aligner to null the input phase error through
the distributed loop. When the loop is locked, the input phase
error between PclkM and SynclkN is within the specification
t
time given in the State Transition Section.
The Phase Detector aligns the rising edge of PclkM to the
rising edge of SynclkN. The duty cycle of the phase detector
input clocks will be within the specification DC
Operating Conditions table. Because the duty cycles of the two
phase detector input clocks will not necessarily be identical,
the falling edges of PclkM and SynclkN may not be aligned
when the rising edges are aligned.
The voltage levels of the PclkM and SynclkN signals are deter-
mined by the controller. The pin VDDIPD is used as the voltage
reference for the phase detector inputs and should be
connected to the output voltage supply of the controller. In
some applications, the DRCG PLL output clock will be used
directly, by bypassing the Phase Aligner. If PclkM and SynclkN
are not used, those inputs must be grounded.
Selection Logic
Table 2 shows the logic for selecting the PLL prescaler and
feedback dividers to determine the multiply ratio for the PLL
from the input Refclk. Divider A sets the feedback and divider
B sets the prescaler, so the PLL output clock frequency is set
by: PLLclk = Refclk*A/B.
ERR,PD
given in the Device Characteristics table after the lock
W133
W158
W159
W161
W167
CY2210
RMC
Pclk
Figure 3. DDLL Including Details of DRCG
Refclk
IN,PD
given in the
W134M/W134S
PLL
M
Gear
Ratio
Logic
N
Phase
Align
D
Synclk
Table 2. PLL Divider Selection
Table 3 shows the logic for enabling the clock outputs, using
the StopB input signal. When StopB is HIGH, the DRCG is in
its normal mode, and Clk and ClkB are complementary outputs
following the Phase Aligner output (PAclk). When StopB is
LOW, the DRCG is in the Clk Stop mode, the output clock
drivers are disabled (set to Hi-Z), and the Clk and ClkB settle
to the DC voltage V
istics table. The level of V
network.
Table 3. Clock Stop Mode Selection
Table 4 shows the logic for selecting the Bypass and Test
modes. The select bits, S0 and S1, control the selection of
these modes. The Bypass mode brings out the full-speed PLL
output clock, bypassing the Phase Aligner. The Test mode
brings the Refclk input all the way to the output, bypassing
both the PLL and the Phase Aligner. In the Output Test mode
(OE), both the Clk and ClkB outputs are put into a
high-impedance state (Hi-Z). This can be used for component
testing and for board-level testing.
Mult0
Clk Stop
Normal
0
0
1
1
Mode
4
S0/S1 StopB
Mult1
DLL
0
1
1
0
RAC
StopB
X,STOP
1
0
Busclk
16
A
9
6
8
X,STOP
W134M
as given in the Device Character-
is set by an external resistor
V
B
2
1
1
3
PAclk
W134M/W134S
X,STOP
Clk
16
A
4
6
8
W134S
Page 4 of 12
V
PAclkB
ClkB
X,STOP
B
1
1
1
3