ICS83052AGILF IDT, Integrated Device Technology Inc, ICS83052AGILF Datasheet - Page 7

• Manufacturer Part Number: ICS83052AGILF
• Description: IC MUX 2:1 SGL ENDED 8-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS83052AGILF

• Number Of Circuits: 2
• Ratio - Input:output: 2:1
• Differential - Input:output: No/No
• Input: LVCMOS, LVTTL
• Output: LVCMOS, LVTTL
• Frequency - Max: 250MHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP
• Frequency-max: 250MHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Single-Ended
• Output Frequency: 250MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVCMOS/LVTTL
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1106; 800-1106-5; 800-1106; 83052AGILF

The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher
IDT
ICS83052I
2:1, SINGLE-ENDED MULTIPLEXER
™
/ ICS
™
2:1, SINGLE-ENDED MULTIPLEXER
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
1k
10k
O
A
FFSET
DDITIVE
100k
F
ROM
P
C
ARRIER
HASE
7
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
than the noise floor of the device. This is illustrated above. The
device meets the noise floor of what is shown, but can actually
be lower. The phase noise is dependant on the input source
and measurement equipment.
F
J
REQUENCY
ITTER
1M
Additive Phase Jitter (Random)
(H
at 155.52MHz (12kHz - 20MHz)
Z
)
10M
ICS83052AGI REV. B JUNE 25, 2008
= 0.18ps (typical)
100M