CY7B991V-2JXC Cypress Semiconductor Corp, CY7B991V-2JXC Datasheet - Page 6

• Manufacturer Part Number: CY7B991V-2JXC
• Description: IC CLK BUFF SKEW 8OUT 32PLCC
• Manufacturer: Cypress Semiconductor Corp
• Type: Buffer/Driverr
• Series: RoboClock™r

Specifications of CY7B991V-2JXC

• Number Of Circuits: 1
• Package / Case: 32-PLCC
• Ratio - Input:output: 8:8
• Differential - Input:output: Yes/Yes
• Input: 3-State
• Output: LVTTL
• Frequency - Max: 80MHz
• Voltage - Supply: 2.97 V ~ 3.63 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 80MHz
• Output Frequency Range: 3.75 MHz to 80 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.97 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1718-5

Operational Mode Descriptions
Figure 2
distribution tree. When all of the function select inputs (×F0, ×F1) are left open, the outputs are aligned and drive a terminated
transmission line to an independent load. The FB input is tied to any output in this configuration and the operating frequency range
is selected with the FS pin. The low skew specification, coupled with the ability to drive terminated transmission lines (with impedances
as low as 50 Ω), enables efficient printed circuit board design.
Figure 4
traces of different lengths. In addition to low skew between
outputs, the LVPSCB is programmed to stagger the timing of its
outputs. The four groups of output pairs are each programmed
to different output timing. Skew timing is adjusted over a wide
range in small increments using the function select pins. In this
configuration, the 4Q0 output is sent back to FB and configured
for zero skew. The other three pairs of outputs are programmed
to yield different skews relative to the feedback. By advancing
the clock signal on the longer traces or retarding the clock signal
on shorter traces, all loads receive the clock pulse at the same
time.
Figure 4
skew (xF1, xF0 = MID) selected. The internal PLL synchronizes
Document Number: 38-07141 Rev. *G
shows the LVPSCB configured as a zero skew clock buffer. In this mode, the CY7B991V is the basis for a low-skew clock
shows a configuration to equalize skew between metal
shows the FB input connected to an output with 0 ns
SYSTEM
CLOCK
SYSTEM
CLOCK
Figure 3. Zero Skew and Zero Delay Clock Driver
Figure 4. Programmable Skew Clock Driver
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
LENGTH L1 = L2 = L3 = L4
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LENGTH L1 = L2
REF
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
L3 < L2 by 6 inches
L4 > L2 by 6 inches
REF
the FB and REF inputs and aligns their rising edges to make
certain that all outputs have precise phase alignment.
Clock skews are advanced by ±6 time units (tU) when using an
output selected for zero skew as the feedback. A wider range of
delays is possible if the output connected to FB is also skewed.
Since “Zero Skew”, +tU, and –tU are defined relative to output
groups, and the PLL aligns the rising edges of REF and FB, wider
output skews are created by proper selection of the xFn inputs.
For example, a +10 tU between REF and 3Qx is achieved by
connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID,
and 3F1 = High. (Since FB aligns at –4 tU, and 3Qx skews to +6
tU, a total of +10 tU skew is realized.) Many other configurations
are realized by skewing both the outputs used as the FB input
and skewing the other outputs.
L1
L2
L3
L4
L1
L2
L3
L4
Z
Z
Z
0
0
Z
0
0
Z
Z
Z
0
Z
0
0
LOAD
0
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
CY7B991V
Page 6 of 17
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