CY7B991V-2JXC Cypress Semiconductor Corp, CY7B991V-2JXC Datasheet - Page 8

IC CLK BUFF SKEW 8OUT 32PLCC

CY7B991V-2JXC

Manufacturer Part Number
CY7B991V-2JXC
Description
IC CLK BUFF SKEW 8OUT 32PLCC
Manufacturer
Cypress Semiconductor Corp
Type
Buffer/Driverr
Series
RoboClock™r
Datasheet

Specifications of CY7B991V-2JXC

Number Of Circuits
1
Package / Case
32-PLCC
Ratio - Input:output
8:8
Differential - Input:output
Yes/Yes
Input
3-State
Output
LVTTL
Frequency - Max
80MHz
Voltage - Supply
2.97 V ~ 3.63 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Frequency-max
80MHz
Output Frequency Range
3.75 MHz to 80 MHz
Supply Voltage (max)
3.63 V
Supply Voltage (min)
2.97 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-1718-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7B991V-2JXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7B991V-2JXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Figure 9
downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay)
necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumulate
low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers in a
series.
Document Number: 38-07141 Rev. *G
shows the CY7B991V connected in series to construct a zero skew clock distribution tree between boards. Delays of the
SYSTEM
CLOCK
DISTRIBUTION
20 MHz
CLOCK
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
FB
REF
FS
Figure 9. Board-to-Board Clock Distribution
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Figure 8. Multi-Function Clock Driver
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
REF
L4
SKEWED –3.125 ns (–4t
L1
L2
80 MHz
L3
Z
ZERO SKEW
0
INVERTED
80 MHz
20 MHz
80 MHz
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Z
Z
Z
0
U
0
0
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
)
Z
0
Z
Z
0
Z
0
0
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CY7B991V
Page 8 of 17
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