CY29940AI Cypress Semiconductor Corp, CY29940AI Datasheet

IC CLK BUFF 1:18 200MHZ 32LQFP

CY29940AI

Manufacturer Part Number
CY29940AI
Description
IC CLK BUFF 1:18 200MHZ 32LQFP
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Buffer (Distribution), Multiplexerr
Datasheet

Specifications of CY29940AI

Package / Case
32-LQFP
Number Of Circuits
1
Ratio - Input:output
1:18
Differential - Input:output
Yes/No
Input
LVCMOS, LVPECL, LVTTL
Output
LVCMOS, LVTTL
Frequency - Max
200MHz
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Frequency-max
200MHz
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Multiply / Divide Factor
1:18
Number Of Clock Inputs
2
Output Logic Level
LVCMOS, LVTTL
Supply Voltage (max)
3.465 V
Supply Voltage (min)
2.375 V
Maximum Operating Temperature
+ 85 C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY29940AI
Manufacturer:
PHILIPS
Quantity:
383
Part Number:
CY29940AI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Cypress Semiconductor Corporation
Document #: 38-07283 Rev. *C
Features
Pin Description
Note:
1.
• 200-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS/LVTTL compatible inputs
• 18 clock outputs: drive up to 36 clock lines
• 60 ps typical output-to-output skew
• Dual or single supply operation:
• Pin compatible with MPC940L, MPC9109
• Available in Commercial and Industrial temperature
• 32-pin LQFP package
5
6
3
9, 10, 11, 13, 14,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
4
8, 16, 29
7, 21
1, 2, 12, 17, 25
Block Diagram
— 3.3V core and 3.3V outputs
— 3.3V core and 2.5V outputs
— 2.5V core and 2.5V outputs
PD = Internal Pull-Down, PU = Internal Pull-up
PECL_CLK#
PECL_CLK
TCLK_SEL
Pin
TCLK
[1]
VDD
PECL_CLK
PECL_CLK#
TCLK
Q(17:0)
TCLK_SEL
VDDC
VDD
VSS
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
0
1
Name
VDDC
PWR
VDDC
I, PU
I, PD
I, PD
I, PD
I/O
18
198 Champion Court
O
Q0-Q17
PECL Input Clock
PECL Input Clock
External Reference/Test Clock Input
Clock Outputs
Clock Select Input. When LOW, PECL clock is selected and when HIGH
TCLK is selected.
3.3V or 2.5V Power Supply for Output Clock Buffers
3.3V or 2.5V Power Supply
Common Ground
Description
The CY29940 is a low-voltage 200-MHz clock distribution buff-
er with the capability to select either a differential LVPECL or
a LVCMOS/LVTTL compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are LVC-
MOS/LVTTL compatible. The eighteen outputs are 2.5V or
3.3V LVCMOS/LVTTL compatible and can drive 50Ω series or
parallel terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:36. Low out-
put-to-output skews make the CY29940 an ideal clock distri-
bution buffer for nested clock trees in the most demanding of
synchronous systems.
PECL_CLK#
PECL_CLK
TCLK_SEL
Pin Configuration
VDDC
TCLK
VDD
VSS
VSS
San Jose
1
2
3
4
5
6
7
8
CY29940
Description
,
CA 95134-1709
Revised April 4, 2006
24
23
22
21
20
19
18
17
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
CY29940
408-943-2600

Related parts for CY29940AI

CY29940AI Summary of contents

Page 1

... VDD 1, 2, 12, 17, 25 VSS Note Internal Pull-Down Internal Pull-up Cypress Semiconductor Corporation Document #: 38-07283 Rev. *C Description The CY29940 is a low-voltage 200-MHz clock distribution buff- er with the capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock ...

Page 2

Maximum Ratings Maximum Input Voltage Relative to V Maximum Input Voltage Relative to V Storage Temperature: ................................ –65° 150°C Operating Temperature: ................................ –40°C to +85°C Maximum ESD Protection............................................... 2 kV Maximum Power Supply: ................................................5.5V Maximum Input Current: ...

Page 3

AC Parameters : V = 3.3V ±5% or 2.5V ±5 Parameter Description F Input Frequency max t PECL_CLK to Q Delay PD </=150 MHz t LVCMOS to Q Delay PD </=150 MHz t Total Jitter J [5, ...

Page 4

Pulse Generator ohm Figure 1. LVCMOS_CLK CY29940 Test Reference for V Differential Pulse Generator ohm Figure 2. PECL_CLK CY29940 Test Reference for V PECL_CLK V PECL_CLK Figure 3. Propagation Delay ...

Page 5

... Ordering Information Part Number CY29940AI 32 Pin LQFP CY29940AIT 32 Pin LQFP – Tape and Reel CY29940AC 32 Pin LQFP CY29940ACT 32 Pin LQFP – Tape and Reel Lead-free CY29940AXI 32 Pin LQFP CY29940AXIT 32 Pin LQFP – Tape and Reel CY29940AXC 32 Pin LQFP CY29940AXCT 32 Pin LQFP – Tape and Reel Document #: 38-07283 Rev ...

Page 6

... Document #: 38-07283 Rev. *C © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 7

Document History Page Document Title: CY29940 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Document Number: 38-07283 Issue REV. ECN NO. Date ** 111094 02/01/02 *A 116776 08/15/02 *B 122875 12/21/02 *C 448379 See ECN Document #: 38-07283 Rev. *C ...

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