IDT49FCT805CTSO8 IDT, Integrated Device Technology Inc, IDT49FCT805CTSO8 Datasheet - Page 6

• Manufacturer Part Number: IDT49FCT805CTSO8
• Description: IC BUFFER/CLOCK DRIVER 20-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 49FCTr
• Type: Fanout Buffer (Distribution)r

Specifications of IDT49FCT805CTSO8

• Number Of Circuits: 2
• Ratio - Input:output: 1:5
• Differential - Input:output: No/No
• Input: TTL
• Output: TTL
• Frequency - Max: 166MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC
• Frequency-max: 166MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 49FCT805CTSO8

TEST CIRCUITS AND WAVEFORMS
OUTPUT
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
IDT49FCT805BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
OUTPUT
INPUT
Generator
NORMALLY
NORMALLY
INPUT
Pulse
CONTROL
OUTPUT
OUTPUT
INPUT
HIGH
LOW
V
IN
CLOSED
SW ITCH
SW ITCH
t
Test Circuits for All Outputs
PLH
OPEN
Enable and Disable Times
t
ENABLE
PLH
R
t
t
T
Pulse Skew - t
PZL
PZH
D.U.T.
t
t
SK
V
R
Package Delay
C C
(p) = t
1.5V
1.5V
3.5V
0V
V
PHL
OUT
t
-
PH Z
SK(P)
t
DISABLE
PLH
50pF
C
t
PHL
F
L
t
PLZ
≤ 2.5ns; t
t
PHL
500
500
0.3V
0.3V
t
F
R
≤ 2.5ns
V
V
3V
1.5V
0V
0V
3.5V
OL
OH
0.8V
2.0V
1.5V
V
1.5V
V
3V
0V
7V
O H
OL
1.5V
V
1.5V
V
3V
0V
OH
O L
6
SWITCH POSITION
DEFINITIONS:
C
R
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
L
T
PACKAGE 2
PACKAGE 1
= Load capacitance: includes jig and probe capacitance.
= Termination resistance: should be equal to Z
OUTPUT 2
OUTPUT
OUTPUT 1
OUTPUT
INPUT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INPUT
Disable HIGH
Enable HIGH
Disable LOW
Enable LOW
Test
t
SK
Part-to-Part Skew - t
t
t
P LH1
(pp) = t
SK
t
PLH1
t
(o) = t
PLH2
t
t
PLH 2
SK(pp)
Output Skew
t
SK(o)
PLH2
PLH2
-
t
-
PLH1
t
P LH 1
OUT
or
SK(PP)
or
of the Pulse Generator.
t
PH L2
t
PH L1
t
PH L2
t
t
PLH1
PH L2
t
Switch
t
Closed
PH L2
SK(pp)
-
GND
t
-
PHL1
t
t
SK(o)
PHL1
V
V
1.5V
1.5V
V
1.5V
V
3V
0V
O H
OL
O H
OL
V
V
V
V
3V
1.5V
1.5V
1.5V
0V
OH
O L
OH
O L