IDT5T93GL04PGGI8 IDT, Integrated Device Technology Inc, IDT5T93GL04PGGI8 Datasheet

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IDT5T93GL04PGGI8

Manufacturer Part Number
IDT5T93GL04PGGI8
Description
IC CLK BUFFER 1:4 LVDS 24-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Fanout Buffer (Distribution), Multiplexerr
Series
TERABUFFER™ IIr
Datasheets

Specifications of IDT5T93GL04PGGI8

Number Of Circuits
1
Ratio - Input:output
2:4
Differential - Input:output
Yes/Yes
Input
CML, eHSTL, HSTL, LVDS, LVPECL, LVTTL
Output
LVDS
Frequency - Max
450MHz
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Frequency-max
450MHz
Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
450MHz
Output Logic Level
LVDS
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (max)
2.7V
Package Type
TSSOP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
24
Quiescent Current
240mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
5T93GL04PGGI8
2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER
TERABUFFER™ II
General Description
The IDT5T93GL04 2.5V differential clock buffer is a
user-selectable differential input to four LVDS outputs. The fanout
from a differential input to four LVDS outputs reduces loading on
the preceding driver and provides an efficient clock distribution
network. The IDT5T93GL04 can act as a translator from a
differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V
LVTTL input can also be used to translate to LVDS outputs. The
redundant input capability allows for
a primary clock source to a secondary clock source up to 450MHz.
Selectable inputs are controlled by SEL. During the switchover,
the output will disable low for up to three clock cycles of the
previously-selected input clock. The outputs will remain low for up
to three clock cycles of the newly-selected clock, after which the
outputs will start from the newly-selected input. A FSEL pin has
been implemented to control the switchover in cases where a
clock source is absent or is driven to DC levels below the minimum
specifications.
The IDT5T9304 outputs can be asynchronously enabled/disabled.
When disabled, the outputs will drive to the value selected by the
GL pin. Multiple power and grounds reduce noise.
Applications
Pin Assignment
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Clock distribution
4.4mm x 7.8mm x 1.0mm package body
FSEL
GND
GND
SEL
24-Lead TSSOP
V
V
PD
Q1
Q1
Q2
Q2
DD
DD
G
G Package
Top View
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
a
glitchless change-over from
A2
GND
Q3
Q3
Q4
A1
A2
V
V
GL
DD
DD
1
Features
Guaranteed low skew: <50ps (maximum)
Very low duty cycle distortion: <100ps (maximum
High speed propagation delay: <2.2ns (maximum)
Up to 450MHz operation
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML or LVDS input interface
Selectable differential inputs to four LVDS outputs
Power-down mode
At power-up, FSEL should be LOW
2.5V V
-40°C to 85°C ambient operating temperature
Available in TSSOP package
DD
IDT5T93GL04 REV. A OCTOBER 21 2008
IDT5T93GL04

Related parts for IDT5T93GL04PGGI8

IDT5T93GL04PGGI8 Summary of contents

Page 1

LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II General Description The IDT5T93GL04 2.5V differential clock buffer is a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding ...

Page 2

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Block Diagram SEL FSEL IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II OUTPUT CONTROL OUTPUT CONTROL 1 OUTPUT CONTROL OUTPUT 0 CONTROL ...

Page 3

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Table 1. Pin Descriptions Name Type A[1:2] Input Adjustable A[1:2] Input Adjustable G Input LVTTL GL Input LVTTL Q[1:2] Output LVDS Q{1:2} Output LVDS SEL Input LVTTL PD Input LVTTL FSEL ...

Page 4

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Function Tables Table 3A. Gate Control Output Table Codntrol Output GL G Q[1: Toggling 0 1 LOW 1 0 Toggling 1 1 HIGH Table 3B. Input Selection Table Selection ...

Page 5

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ Electrical Characteristics Table 4A. LVDS Power Supply DC Characteristics Symbol Parameter Quiescent DDQ Power Supply Current Total Power I TOT V Supply Current DD Total Power Down ...

Page 6

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Table 4D. LVDS DC Characteristics Symbol Parameter Differential Output Voltage for the V OT(+) True Binary State Differential Output Voltage for the V OT(–) False Binary State Change in V Between ...

Page 7

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Table 5B. eHSTL AC Differential Input Characteristics, T Symbol Parameter (1) V Input Signal Swing DIF V Differential Input Signal Crossing Point X D Duty Cycle H V Input Timing Measurement ...

Page 8

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Table 5E. AC Differential Input Characteristics Symbol Parameter ( Differential Voltage DIF V Differential Input Cross Point Voltage X V Common Mode Input Voltage Range CM V Input Voltage ...

Page 9

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Differential AC Timing Waveforms Output Propagation and Skew Waveforms 1/ [1:2] [1:2] t PLH SK( NOTE 1: Pulse skew is calculated ...

Page 10

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Glitchless Output Operation with Switching Input Clock Selection SEL When SEL changes, the output clock goes LOW ...

Page 11

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II FSEL Operation for When Opposite Clock Dies 1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this ...

Page 12

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Power Down Timing NOTE recommended that outputs be disabled before enterning power-down mode. ...

Page 13

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Test Circuits and Conditions Test Circuit for Differential Input V IN Pulse Generator V IN Table 6A. Differential Input Test Conditions Symbol V = 2.5V ± 0. Crossing of ...

Page 14

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Test Circuit for DC Outputs and Power Down Tests V A Pulse Generator D.U.T. A Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing A Pulse Generator D.U.T. A Table 6B. ...

Page 15

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Ordering Information Table 7. Ordering Information XX XXXXX Package Device Type IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ Process I PG PGG 5T93GL04 15 - +85 C (Industrial) ...

Page 16

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Revision History Sheet Rev Table Page Description of Change A T5E 8 AC Characteristics Table - added Rise/Fall Time spec. IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II IDT5T93GL04 REV. A OCTOBER ...

Page 17

IDT5T93GL04 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 ...

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