ICS889872AKLF IDT, Integrated Device Technology Inc, ICS889872AKLF Datasheet

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ICS889872AKLF

Manufacturer Part Number
ICS889872AKLF
Description
IC BUFFER/DIVIDER HS 16-VFQFPN
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution), Dividerr
Datasheet

Specifications of ICS889872AKLF

Number Of Circuits
1
Ratio - Input:output
1:3
Differential - Input:output
Yes/Yes
Input
CML, LVDS, LVPECL
Output
LVDS
Frequency - Max
2GHz
Voltage - Supply
2.375 V ~ 2.625 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-VFQFN
Frequency-max
2GHz
Number Of Outputs
6
Operating Supply Voltage (max)
2.625V
Operating Temp Range
-40C to 85C
Propagation Delay Time
0.75ns
Operating Supply Voltage (min)
2.375V
Mounting
Surface Mount
Pin Count
16
Operating Supply Voltage (typ)
2.5V
Package Type
VFQFPN EP
Input Frequency
>1600MHz
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
889872AKLF
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER
W/INTERNAL TERMINATION
Block Diagram
General Description
dividers. The clock input has internal termination resistors,
allowing it to interface with several differential signal types while
minimizing the number of required external components. The
device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
nDISABLE
HiPerClockS™
nRESET/
ICS
V
REF_AC
nIN
S1
S0
V
IN
T
50Ω
50Ω
The ICS889872 is a high speed Differential-to-
LVDS Buffer/Divider w/Internal Termination and is a
member of the HiPerClockS™ family of high
performance clock solutions from IDT. The
ICS889872 has a selectable ÷2, ÷4, ÷8, ÷16 output
Decoder
Enable
FF
Enable
÷2, ÷4,
÷8, ÷16
MUX
QA
nQA
QB0
nQB0
QB1
nQB1
1
Features
Pin Assignment
Three LVDS outputs
Frequency divide select options: ÷4, ÷6: >2GHz,
IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
Output frequency: >2GHz
Cycle-to-cycle jitter: 1ps (typical)
Total jitter: 10ps (typical)
Output skew: 7ps (typical), QA/nQA outputs
Part-to-part skew: 250ps (typical)
Propagation Delay: 750ps (typical), QA/nQA outputs
Full 2.5V supply mode
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
÷8, ÷16: >1.6GHz
3mm x 3mm x 0.925mm package body
nQB0
nQB1
QB0
QB1
16-Lead VFQFN
1
2
3
4
ICS889872
16 15 14 13
K Package
5
Top View
6
7
ICS889872AK REV. B JULY 10, 2008
8
12
11
10
9
PRELIMINARY
IN
V
V
nIN
T
REF_AC
ICS889872

Related parts for ICS889872AKLF

ICS889872AKLF Summary of contents

Page 1

DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION General Description The ICS889872 is a high speed Differential-to- ICS LVDS Buffer/Divider w/Internal Termination and is a member of the HiPerClockS™ family of high HiPerClockS™ performance clock solutions from IDT. The ICS889872 has a selectable ÷2, ...

Page 2

ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION Table 1. Pin Descriptions Number Name 1, 2 QB0, nQB0 Output 3, 4 QB1, nQB1 Output 5, 6 QA, nQA Output Power DD nRESET/ 8 Input nDISABLE 9 nIN Input 10 V ...

Page 3

ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION Function Tables Table 3A. Control Input Function Table Input Outputs nRESET QA, QBx 0 Disabled; LOW 1 Enabled NOTE: After nRESET switches, the clock outputs are disabled or enabled following a falling input clock edge ...

Page 4

ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions ...

Page 5

ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION Table 4C. Differential DC Characteristics, V Symbol Parameter R Differential Input Resistance IN V Input High Voltage IH V Input Low Voltage IL V Input Voltage Swing IN V Differential Input Voltage Swing DIFF_IN I ...

Page 6

ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION Parameter Measurement Information V DD 2.5V±5% POWER SUPPLY LVDS + – Float GND LVDS Output Load AC Test Circuit Par t 1 nQx Qx Par t 2 nQy Qy tsk(pp) Part-to-Part Skew nQA, nQB[0:1] QA, ...

Page 7

ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION Parameter Measurement Information, continued OUT 400mV (typical) Single-Ended & Differential Input Voltage Swing V DD LVDS DC Input ➤ Offset Voltage Setup IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION nQA, nQB[0:1] ...

Page 8

ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the ...

Page 9

ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION 2.5V LVPECL Input with Built-In 50 The IN /nIN with built-in 50Ω terminations accept LVDS, LVPECL, CML and other differential signals. Both signals must meet the V and V input requirements. Figures ...

Page 10

ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the ...

Page 11

ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION 2.5V LVDS Driver Termination Figure 5 shows a typical termination for LVDS driver in characteristic impedance of 100Ω differential (50Ω single) 2.5V LVDS Driver 100Ω Differential Transmission Line Figure 5. Typical LVDS Driver Termination IDT™ ...

Page 12

ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION Power Considerations This section provides information on power dissipation and junction temperature for the ICS889872. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS889872 is the sum ...

Page 13

ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION Reliability Information Table 7. θ vs. Air Flow Table for a 16 Lead VFQFN JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS889872 is: 323 Pin compatible ...

Page 14

ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION Ordering Information Table 9. Ordering Information Part/Order Number Marking 889872AK 872A 889872AKT 872A 889872AKLF TBD 889872AKLFT TBD NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and ...

Page 15

ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION Contact Information: www.IDT.com Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are ...

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