NB7VQ58MMNTXG ON Semiconductor, NB7VQ58MMNTXG Datasheet - Page 2

• Manufacturer Part Number: NB7VQ58MMNTXG
• Description: IC CLOCK/DATA MULTIPLEXER 16QFN
• Manufacturer: ON Semiconductor
• Series: GigaComm™r
• Type: Multiplexer , Datar

Specifications of NB7VQ58MMNTXG

• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, LVPECL
• Output: CML
• Frequency - Max: 7GHz
• Voltage - Supply: 1.71 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TFQFN Exposed Pad
• Frequency-max: 7GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
Table 3. PIN DESCRIPTION
Pin
Table 1. EQualizer ENable FUNCTION
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
−
EQEN
if no signal is applied on IN0/IN0, IN1/IN1 inputs, then the device will be susceptible to self−oscillation. Q/Q outputs have internal 50 W source
termination resistors.
IN0
IN0
IN1
IN1
0
1
Figure 1. Pin Configuration
Name
EQEN
VCC
GND
GND
VCC
GND
GND
VT1
SEL
VT0
IN0
IN0
IN1
IN1
EP
Q
Q
1
2
3
4
INn / INn Inputs By−pass the EQualizer section
VT0 GND GND
VT1 SEL EQEN VCC
16
LVPECL, CML, LVDS Input
LVPECL, CML, LVDS Input
LVPECL, CML, LVDS Input
LVPECL, CML, LVDS Input
5
LVTTL/LVCMOS Input
NB7VQ58M
Inputs flow through the EQualizer
15
LVCMOS Input
6
CML Output
CML Output
14
I/O
7
−
−
−
−
−
−
−
−
−
Function
VCC
13
8
(Top View)
12
11
10
9
Noninverted Differential Input (Note 1)
Inverted Differential Input (Note 1)
Noninverted Differential Input (Note 1)
Inverted Differential Input (Note 1)
Internal 50 W Termination Pin for IN1/IN1
SEL Input. Low for IN0 inputs, High for IN1 inputs. (Note 1) Pin will default HIGH when
left open (has internal pullup resistor)
Equalizer Enable Input; pin will default LOW when left open (has internal pulldown
resistor)
Positive Supply Voltage (Note 2)
Inverted Differential Output
Negative Supply Voltage
Negative Supply Voltage
Noninverted Differential Output
Positive Supply Voltage (Note 2)
Negative Supply Voltage
Negative Supply Voltage
Internal 50 W Termination Pin for IN0/IN0
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and must be
electrically and thermally connected to GND on the PC board.
Q
GND
GND
Q
Exposed
Pad (EP)
http://onsemi.com
LVPECL, LVDS, CML
Multi−Level Inputs
2
Table 2. SELect FUNCTION TRUTH TABLE
GND
VT0
VT1
VCC
IN0
IN0
IN1
IN1
(Equalizier Enable)
SEL
50 W
50 W
50 W
50 W
SEL
Figure 2. Detailed Block Diagram
H
L
Description
75 kW
EQEN
V
CC
D0
D1
Q
Mux
0
1
2:1
75 kW
EQ
Mux
0
1
2:1
D0
D1
Q
Q
Q