NB7V585MMNR4G ON Semiconductor, NB7V585MMNR4G Datasheet - Page 2

• Manufacturer Part Number: NB7V585MMNR4G
• Description: IC CLK/DATA BUFFER/XLATOR 32-QFN
• Manufacturer: ON Semiconductor
• Series: GigaComm™r
• Type: Fanout Buffer (Distribution), Multiplexer , Translator, Datar

Specifications of NB7V585MMNR4G

• Number Of Circuits: 1
• Ratio - Input:output: 2:6
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, LVPECL
• Output: CML
• Frequency - Max: 7GHz
• Voltage - Supply: 1.71 V ~ 2.625 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TFQFN Exposed Pad
• Frequency-max: 7GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
2. All V
Table 2. PIN DESCRIPTION
VREFAC0
VREFAC1
11, 16, 18
23, 25, 30
if no signal is applied on INn/INn input, then, the device will be susceptible to self−oscillation. Qn/Qn outputs have internal 50 W source
termination resistors.
29, 28
27, 26
22, 21
20, 19
15, 14
13, 12
24, 32
9, 17,
Pin
1,4
5,8
2,6
IN0
31
10
VT0
VT1
IN0
IN1
IN1
3
7
−
CC
Figure 1. 32−Lead QFN Pinout (Top View)
and GND pins must be externally connected to a power supply for proper operation.
1
2
3
4
5
6
7
8
32
VREFAC0
VREFAC1
9
VT0, VT1
IN0, IN0
IN1, IN1
Q0, Q0
Q1, Q1
Q2, Q2
Q3, Q3
Q4, Q4
Q5, Q5
Name
GND
VCC
SEL
NC
EP
31
10
30
11
NB7V585M
LVTTL/LVCMOS
LVPECL, CML,
29
12
CML Output
CML Output
CML Output
LVDS Input
Input
28
13
I/O
−
−
−
−
27
14
26
15
Non−inverted, Inverted, Differential Inputs
Internal 100 W Center−tapped Termination Pin for IN0/IN0 and IN1/IN1
Input Select pin; LOW for IN0 Inputs, HIGH for IN1 Inputs; defaults HIGH when left open
No Connect
Positive Supply Voltage.
Non−inverted, Inverted Differential Outputs (Note 1).
Non−inverted, Inverted Differential Outputs (Note 1).
Non−inverted, Inverted Differential Outputs (Note 1).
Negative Supply Voltage, connected to Ground
Output Voltage Reference for Capacitor−Coupled Inputs, only
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and must be electric-
ally and thermally connected to GND on the PC board.
25
16
Exposed Pad
(EP)
24
23
22
21
20
19
18
17
http://onsemi.com
GND
VCC
Q2
Q2
Q3
Q3
VCC
GND
2
Table 1. INPUT SELECT FUNCTION TABLE
*Defaults HIGH when left open.
SEL*
Description
0
1
CLK Input Selected
IN0
IN1