FS6377-01G-XTD ON Semiconductor, FS6377-01G-XTD Datasheet

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... Accepts 5MHz to 27MHz crystal resonators • Commercial and industrial temperature ranges offered 2.0 General Description The FS6377 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three 2 I C-programmable phase locked loops (PLLs) feeding four programmable muxes and post dividers provide a high degree of flexibility. ...

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... FS6377 Table 1: Pin Descriptions Pin Type Name SDA SEL_CD VSS 5 AI XIN 6 AO XOUT VDD ADDR 10 DO CLK_D 11 P VSS 12 DO CLK_C 13 DO CLK_B 14 P VDD 15 DO CLK_A SCL Key: AI: Analog Input Analog Output Digital Input; DI DI-3 = Three-level Digital Input Digital Output Power/Ground Active Low Pin ...

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... FS6377 3.0 Functional Block Description 3.1 Phase Locked Loops (PLLs) Each of the three on-chip PLLs is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a desired frequency by a ratio of integers. This frequency multiplication is exact. As shown in Figure 3, each PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), and a feedback divider ...

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... FS6377 For example, a fixed divide-by-eight could be used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective modulus of the entire feedback divider to multiples of eight. This limitation would restrict the ability of the PLL to achieve a desired input- frequency-to-output frequency ratio without making both the reference and feedback divider values comparatively large. ...

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... SEL_CD pin. 4.0 Device Operation The FS6377 powers up with all internal registers cleared to zero, delivering the crystal frequency to all outputs. For operation to occur, the registers must be loaded in a most significant-bit (MSB) to least-significant-bit (LSB) order. The register mapping of the FS6377 is ...

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... FS6377 4.3 Oscillator Overdrive For applications where an external reference clock is provided (and the crystal oscillator is not required), the reference clock should be connected to XOUT and XIN should be left unconnected (float). For best results, make sure the reference clock signal is as jitter-free as possible, can drive a 40pF load with fast rise and fall times and can swing rail-to-rail. If the reference clock is not a rail-to-rail signal, the reference must be AC coupled to XOUT through a 0.01µ ...

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... FS6377 5.1.5. Acknowledge When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account. ...

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... FS6377 is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write up to sixteen bytes of data into the addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the device between each byte of data must occur before the next data byte is sent. ...

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... FS6377 Figure 5: Random Register Write Procedure Figure 6: Random Register Read Procedure Figure 7: Sequential Register Write Procedure Figure 8: Sequential Register Read Procedure Rev Page www.onsemi.com ...

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... FS6377 6.0 Programming Information Table 3: Register Map Address BIT 7 BIT 6 MUX_D2[1:0] Byte 15 (selected via SEL_CD = 1 POST_D2[3:0] Byte 14 (selected via SEL_CD = 1) POST_D1[3:0] Byte 13 (selected via SEL_CD = 0) POST_B[3:0] Byte 12 MUX_D1[1:0] Byte 11 (selected via SEL_CD = 0) FBKDIV_C2[7:3] M-Counter Byte 10 (selected via SEL_CD pin = 1) Byte 9 MUX_C1[1:0] ...

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... FS6377 6.2 Power-Down All power-down functions are controlled by enable bits. The bits select which portions of the device to power-down when the PD input is asserted. Table 4: Power-Down Bits Name Description Power-Down PLL A Bit = 0 Power on PDPLL_A (Bit 21) Bit = 1 Power off Power-Down PLL B Bit = 0 Power on PDLL_B ...

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... FS6377 Table 6: Divider Control Bits Name Description POST_A[3:0] POST divider A (see Table 7) (Bits 99-96) POST_B[3:0] POST divider B (see Table 7) (Bits 103-100) POST divider C1 (see Table 7) POST_C1[3:0] (Bits 107-104) selected when the SEL_CD pin = 0 POST divider C2 (see Table 7) POST_C2[3:0] (Bits 115-112) selected when the SEL_CD pin = 1 ...

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... FS6377 Table 8: PLL Tuning Bits Name Description Loop Filter Time Constant A Bit = 0 Short time constant: 7µs LFTC_A (Bit 20) Bit = 1 Long time constant: 20µs Loop Filter Time Constant B selected when the SEL_CD pin = 0 Bit = 0 Short time constant: 7µs LFTC_B (Bit 44) Bit = 1 Long time constant: 20µs ...

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... FS6377 Table 9: Mux Select Bits Name Description Mux A Frequency Select Bit 23 Bit MUX_A[1: (Bits 23-22 Mux B Frequency Select Bit 47 Bit MUX_B[1: (Bits 47-46 Mux C1 Frequency Select selected when the SEL_CD pin = 0 Bit 71 Bit MUX_C1[1: (Bits 71-70 Mux C2 Frequency Select selected when the SEL_CD pin = 1 ...

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... FS6377 7.0 Electrical Specifications Table 10: Absolute Maximum Ratings Parameter Supply voltage ground) SS Input voltage, dc Output voltage, dc Input clamp current < > Output clamp current < > Storage temperature range (non-condensing) Ambient temperature range, under bias Junction temperature Re-flow solder profile Input static discharge voltage protection (MIL-STD 883E, Method 3015.7) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device ...

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... FS6377 Table 12: DC Electrical Specifications (continued) Mode and Frequency Select Inputs (ADDR, SEL_CD) High-level input voltage Low-level input voltage High-level input current Low-level input current (pull-up) Crystal Oscillator Feedback (XIN) Threshold bias voltage High-level input current Low-level input current Crystal loading capacitance* ...

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... FS6377 Figure 10: Dynamic Current vs. Output Frequency Rev Page www.onsemi.com ...

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... FS6377 Table 13: AC Timing Specifications Parameter Symbol Overall Output frequency VCO frequency* f VCO VCO gain* A VCO Loop filter time constant* Rise time Fall time Tristate enable delay PZL PZH Tristate disable delay PZL PZH Clock stabilization time* t STB Divider Modulus Feedback divider ...

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... FS6377 Table 13: AC Timing Specifications continued Clock Outputs (PLL_C clock via CLK_C pin) Approximate Duty cycle* t Jitter, long term (σy(τ))* j(LT) Jitter, period (peak-peak)* t j(ΔP) Clock Outputs (Crystal Oscillator via CLK_D pin) Approximate Duty cycle* t Jitter, long term (σy(τ))* ...

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... FS6377 8.0 Package Information – For Both ‘Green’ and ‘No-Green’ Table 15: 16-pin SOIC (0.150") Package Dimensions Dimensions Inches Millimeters Min. Max. Min. Max. A 0.061 0.068 1.55 1.73 A1 0.004 0.0098 0.102 0.249 A2 0.055 0.061 1.40 1.55 B 0.013 0.019 0.33 0. ...

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... Lead inductance, self Lead inductance, mutual Lead capacitance, bulk 9.0 Ordering Information Part Number Package 16-pin (0.150”) SOIC FS6377-01G-XTD (small outline package) ‘Green’ or lead-free packaging 16-pin (0.150”) SOIC FS6377-01G-XTP (small outline package) ‘Green’ or lead-free packaging 16-pin (0.150”) SOIC ...

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... FS6377 10.2.1. Example Programming Type a value for the crystal resonator frequency in MHz in the reference crystal box. This frequency provides the basis for all of the PLL calculations that follow. Next, click on the PLL A box. A pop-up screen similar to Figure 15 should appear. Type in a desired output clock frequency in MHz, set the operating voltage (3 ...

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... FS6377 For a 100MHz output, the VCO should ideally operate at a higher frequency, and the reference and feedback dividers should be as small as possible. In this example, highlight Solution #7. Notice the VCO operates at 200MHz with a post divider of two to obtain an optimal 50 percent duty cycle. Now choose which mux and post divider to use (that is, choose an output pin for the 100MHz output). Selecting A places the PostDiv value in Solution #7 into post divider A and switches mux A to take the output of PLL A ...

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... FS6377 Click on PLL C1 to open the PLL screen. Set a desired frequency, however, now choose the post divider B as the output divider. Notice the post divider box has split in two (as shown in Figure 16). The post divider B box now shows that the divider is dependent on the setting of the SEL_CD pin for as long as mux B is the PLL C output ...