CY2291FI Cypress Semiconductor Corp, CY2291FI Datasheet

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... MHz – 25 MHz (external crystal) 1 MHz – 30 MHz (reference clock) CY2291F 8 10 MHz – 25 MHz (external crystal) 1 MHz – 30 MHz (reference clock) CY2291FI 8 10 MHz – 25 MHz (external crystal) 1 MHz – 30 MHz (reference clock) Logic Block Diagram 32XIN 32XOUT XTALIN ...

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Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Output Configuration ....................................................... 4 Power Saving Features .................................................... 4 CyClocks Software ........................................................... 4 Cypress FTG Programmer ............................................... 4 Custom Configuration Request Procedure .................... 4 Maximum Ratings ............................................................. 5 Operating Conditions....................................................... 5 Electrical ...

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Pinouts Pin Definitions Name Pin Number 32XOUT 1 32K 2 CLKC 3 VDD 4, 16 GND 5 [1] XTALIN 6 [1, 2] XTALOUT 7 XBUF 8 CLKD 9 CPUCLK 10 CLKB 11 CLKA 12 CLKF ...

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Output Configuration The CY2291 has five independent frequency sources on-chip. These are the 32-kHz oscillator, the reference oscillator, and three Phase-locked loops (PLLs). Each PLL has a specific function. The System PLL (SPLL) drives the CLKF output and provides fixed ...

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... DD Document Number: 38-07189 Rev. *E Max. soldering temperature (10 sec).......................... 260 C Junction temperature.................................................. 150 C Package power dissipation....................................... 750 mW Static discharge voltage............................................. (per MIL-STD-883, Method 3015) Part Numbers All All All CY2291/CY2291F CY2291I/CY2291FI All All All All Conditions ...

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... Except crystal pins Except crystal pins –0 +0 Three-state outputs Max operation DD DD Shutdown active, CY2291I/CY2291FI excluding V BATT = 3.0 V BATT +F +2•F )+0.27•( CPLL UPLL SPLL CLKA CLKB CLKC CY2291 Min Typ Max Unit   2.4 V   ...

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... Document Number: 38-07189 Rev. *E Conditions Except crystal pins Except crystal pins –0 +0 Three-state outputs max., 3.3V operation DD DD Shutdown active, CY2291I/CY2291FI excluding V BATT = 3.0 V BATT Description CY2291 CY2291F [16]  [16]  [17] [17] [18, +F +2•F )+0.27•( CPLL UPLL SPLL CLKA CLKB CLKC ...

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Switching Characteristics, Commercial 5.0 V Parameter Name [21] t Peak-to-peak period jitter (t Clock jitter 9A clock period (f [21] t Peak-to-peak period jitter (t Clock jitter 9B (4 MHz < f [21] t Peak-to-peak period jitter Clock jitter 9C ...

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Switching Characteristics, Commercial 3.3 V Parameter Name [27] t Peak-to-peak period jitter (t Clock jitter 9A clock period (f [27] t Peak-to-peak period jitter (t Clock jitter 9B < f < 16 MHz) OUT [27] t Peak-to-peak period jitter Clock ...

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... Max. – t min.),% < 4 MHz) OUT Max. – t min.) (4 MHz 9B 9B < 50 MHz) OUT CY2291I CY2291FI CY2291 Min Typ Max Unit  11.1 13000 ns (90 MHz) (76.923 kHz)  12.5 13000 ns (80 MHz) (76.923 kHz)  40% 50% 60%  ...

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... Max. – t min.),% < 4 MHz) OUT Max. – t min.) (4 MHz 9B 9B < 50 MHz) OUT > 50 MHz) OUT CY2291I CY2291FI CY2291 Min Typ Max Unit  15 13000 ns (66.6 MHz) (76.923 kHz)  16.66 13000 ns (60 MHz) (76.923 kHz)  40% ...

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Switching Waveforms Figure 2. All Outputs, Duty Cycle and Rise/Fall Time OUTPUT ALL THREE-STATE OUTPUTS CLK OUTPUT RELATED CLK OLD SELECT SELECT CPU Test Circuit V DD 0.1  0.1 F Note 40. The CY2291 ...

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Ordering Information Ordering Code Pb-free CY2291FX 20-Pin SOIC CY2291FXT 20-Pin SOIC – Tape and reel Possible Configuration [41] Ordering Code Pb-free CY2291SXC–XXX 20-Pin SOIC CY2291SXC–XXXT 20-Pin SOIC – Tape and reel CY2291SXL–XXX 20-Pin SOIC CY2291SXL–XXXT 20-Pin SOIC – Tape and ...

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Package Diagram Figure 6. 20-Pin (300 MIL) SOIC Package Outline Document Number: 38-07189 Rev. *E CY2291 51-85024 *D Page [+] Feedback ...

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Acronyms Acronym Description CLKIN Clock input CMOS complementary metal oxide semiconductor OE Output enable PLL Phase locked loop SPLL System Phase locked loop PPM Parts per million FTG Frequency time generator FAE Field application engineer Document Conventions Units of Measure ...

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... Updated template. Added Note “Not recommended for new designs.” Removed part number CY2291F, CY2291FT, CY2291SC-XXX, CY2291SC-XXXT, CY2291SI-XXX, CY2291SI-XXXT, CY2291SL-XXX, CY2291SL-XXXT, CY2291FIT, CY2291SXI-XXX, CY2291SXI-XXXT, CY2291FXI and CY2291FXIT. Changed CyClocks reference to include CyberClocks. Changed Lead-free to Pb-free. Updated Package diagram 51-85024 *B to 51-85024 *C. ...

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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...