AD9516-0BCPZ Analog Devices Inc, AD9516-0BCPZ Datasheet - Page 52

• Manufacturer Part Number: AD9516-0BCPZ
• Description: IC CLOCK GEN 2.8GHZ VCO 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-0BCPZ

• Pll: Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.95GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.95GHz
• Clock Ic Type: Clock Generator
• Ic Interface Type: Serial
• Frequency: 2.8GHz
• No. Of Outputs: 14
• No. Of Multipliers / Dividers: 32
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9516-0
Table 49. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
R/W
SCLK
SCLK
SCLK
SDIO
SDIO
SDIO
SDO
CS
CS
CS
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DON’T CARE
SCLK
SDIO
CS
DON’T CARE
I14
W1
R/W
DON'T CARE
DON'T CARE
W1
R/W
A0 A1 A2 A3
W0
W1
16-BIT INSTRUCTION HEADER
A12
I13
W0
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
W0
A12
t
S
R/W
A11 A10 A9 A8 A7
A4
I12
A12 = 0
16-BIT INSTRUCTION HEADER
16-BIT INSTRUCTION HEADER
t
A5 A6 A7 A8
DS
Figure 66. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
W1
Figure 64. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data
Figure 65. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data
Figure 68. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data
SCLK
SDIO
W0
SDO
t
DH
CS
I11
A11 = 0
Figure 67. Timing Diagram for Serial Control Port Register Read
A12
A6 A5
A9 A10 A11 A12
A11
t
HI
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
A4 A3 A2
REGISTER (N) DATA
I10
A10 = 0
DATA BIT N
A10
t
LO
W0
t
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DV
A9
A1 A0
t
W1
CLK
I9
A9
R/W
A8
D0
D7 D6 D5 D4 D3
DATA BIT N – 1
REGISTER (N – 1) DATA
I8
A8
A7
D1
REGISTER (N) DATA
REGISTER (N) DATA
D2 D3 D4
A6
I7
A7
A5
I6
A6
D2 D1 D0 D7
D5 D6 D7
D4
REGISTER (N – 2) DATA
I5
A5
D3
D0
I4
A4
D2
D6 D5
REGISTER (N – 1) DATA
D1 D2
REGISTER (N + 1) DATA
D1
I3
A3
D4 D3 D2
D3 D4 D5
REGISTER (N – 3) DATA
D0
I2
A2
t
C
D1 D0
D6
DON'T CARE
DON'T CARE
I1
A1
D7
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DON’T CARE
DON’T
LSB
I0
A0
CARE