MPC9772FA IDT, Integrated Device Technology Inc, MPC9772FA Datasheet - Page 7

• Manufacturer Part Number: MPC9772FA
• Description: IC PLL CLK GEN 1:12 3.3V 52-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9772FA

• Pll: Yes with Bypass
• Input: LVCMOS, Crystal
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:18
• Differential - Input:output: No/No
• Frequency - Max: 240MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 240MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
MPC9772
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
Table 10. AC Characteristics (V
10. Cycle jitter is valid for all outputs in the same divider configuration. See
11. Period jitter is valid for all outputs in the same divider configuration. See
12. I/O jitter is valid for a VCO frequency of 400 MHz. See
13. –3 dB point of PLL transfer characteristics.
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. In bypass mode, the MPC9772 divides the input reference clock.
3. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: f
4. The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio:
5. Calculation of reference duty cycle limits: DC
6. The MPC9772 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t
7. Static phase offset depends on the reference frequency. t
8. Excluding QSYNC output. See application section for part-to-part skew calculation.
9. Output duty cycle is DC = (0.5 ± 200 ps ⋅ f
Symbol
t
t
t
t
JIT(PER)
PLZ, HZ
PZL, LZ
t
t
JIT(CC)
t
t
JIT(∅)
SK(O)
LOCK
f
be guaranteed if t
R
BW
t
DC
XTAL(min, max)
(∅)
, t
F
Propagation Delay (static phase offset)
CCLK to FB_IN
Output-to-output Skew
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle Jitter
Period Jitter
I/O Phase Jitter RMS (1 σ)
PLL closed loop bandwidth
Maximum PLL Lock Time
= f
VCO(min, max)
R
, t
F
(11)
are within the specified range.
Characteristics
f
REF
(9)
6.25 MHz < f
65.0 MHz < f
(10)
=50 MHz and feedback=÷8
÷ (M ⋅ VCO_SEL) and 10 MHz ≤ f
(8)
CC
(12)
(13)
= 3.3 V ± 5%, T
within QA outputs
within QB outputs
within QC outputs
REF
REF
OUT
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
÷4 feedback
÷6 feedback
÷8 feedback
÷4 feedback
÷6 feedback
÷8 feedback
REF,MIN
< 65.0 MHz
)
< 125 MHz
all outputs
⋅
(7)
100%. E.g. the DC range at f
= t
A
Applications Information
PW,MIN
= –40° to +85°C)
(∅)
(T÷2) – 200
[s] = t
–166
⋅ f
Min
0.1
XTAL
–3
–4
REF
(∅)
7
TT
≤ 25 MHz.
[°] ÷ (f
⋅ 100% and DC
.
Applications Information
Applications Information
1.20 – 3.50
0.70 – 2.50
0.50 – 1.80
0.45 – 1.20
0.30 – 1.00
0.25 – 0.70
0.20 – 0.55
0.17 – 0.40
0.12 – 0.30
0.11 – 0.28
REF
(1), (2)
T ÷ 2
OUT
Typ
150
⋅ 360°).
section for I/O jitter vs. VCO frequency.
= 100 MHz is 48% < DC < 52%. T = output period.
, continued on next page
REF,MAX
T
to +70°C
A
= 0°C
(T÷2) + 200
= 100% – DC
+166
Max
100
100
100
250
200
150
section for more details.
1.0
+3
+4
11
86
13
88
16
19
21
22
27
30
10
section for more details.
8
8
T
to +85°C
A
= –40°C
MPC9772 REV 6 FEBRUARY 7, 2007
(∅)
, t
REF
REF, MIN
PW,MIN
= f
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
VCO
ps
ps
ps
ps
ps
ps
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
°
°
, DC and f
.
÷ (M Þ VCO_SEL).
PLL locked
0.55 to 2.4 V
(VCO=400 MHz)
Condition
MAX
can only