ICS9DB306BLILFT IDT, Integrated Device Technology Inc, ICS9DB306BLILFT Datasheet

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ICS9DB306BLILFT

Manufacturer Part Number
ICS9DB306BLILFT
Description
IC JITTER ATTENUATOR 28-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Jitter Attenuatorr
Datasheet
1.ICS9DB306BLLFT.pdf (17 pages)

Specifications of ICS9DB306BLILFT

Input
HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output
LVPECL
Frequency - Max
140MHz
Voltage - Supply
2.97 V ~ 3.63 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-TSSOP
Frequency-max
140MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
9DB306BLILFT
B
ICS9DB306BL REVISION C AUGUST 13, 2009
G
bandwidth, high phase noise PLL frequency synthesizer. In
these systems, a zero delay buffer may be required to attenuate
high frequency random and deterministic jitter components from
the PLL synthesizer and from the system board. The ICS9DB306
has 2 PLL bandwidth modes. In low bandwidth mode, the PLL
loop BW is about 500kHz and this setting will attenuate much of
the jitter from the reference clock input while being high enough
to pass a triangular input spread spectrum profile. There is also
a high bandwidth mode which sets the PLL bandwidth at 1MHz
which will pass more spread spectrum modulation.
For serdes which have x30 reference multipliers instead of x25
multipliers, 5 of the 6 PCI Express outputs (PCIEX1:5) can be
set for 125MHz instead of 100MHz by configuring the appropriate
frequency select pins (FS0:1). Output PCIEX0 will always run at
the reference clock frequency (usually 100MHz) in desktop PC
PCI Express Applications.
BYPASS
HiPerClockS™
IC S
LOCK
nOE0
nCLK
nOE1
ENERAL
CLK
D
The ICS9DB306 is a high performance 1-to-6
Differential-to-LVPECL Jitter Attenuator designed for
use in PCI Express™ systems. In some PCI Express
systems, such as those found in desktop PCs, the
PCI Express clocks are generated from a low
IAGRAM
D
Detector
Phase
Buffer
ESCRIPTION
Internal Feedback
PCI Express Jitter Attenuator
Loop
Filter
÷5
1 Disabled
0 Enabled
1 Disabled
0 Enabled
VCO
0 ÷4
1 ÷5
FS0
0 ÷5
1 ÷4
FS1
÷5
0
1
0
1
0
1
1
F
Six differential LVPECL output pairs
One differential clock input
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 140MHz
Input frequency range: 90MHz - 140MHz
VCO range: 450MHz - 700MHz
Output skew: 135ps (maximum)
Cycle-to-Cycle jitter: 30ps (maximum)
RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 3ps (typical)
3.3V operating supply
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Industrial temperature information available upon request
EATURES
PCIEXT0
nPCIEXC0
PCIEXT1
nPCIEXC1
PCIEXT2
nPCIEXC2
PCIEXT3
nPCIEXC3
PCIEXT4
nPCIEXC4
PCIEXT5
nPCIEXC5
P
2009 Integrated Device Technology, Inc.
IN
5.3mm x 10.2mm x 1.75mm
PCIEXC1
PCIEXC2
PCIEXC3
PCIEXC4
PCIEXT1
PCIEXT2
PCIEXT3
PCIEXT4
4.4mm x 9.7mm x 0.925mm
28-Lead TSSOP, 173-MIL
28-Lead, 209-MIL SSOP
A
nOE0
nOE1
V
V
V
V
SSIGNMENT
CC
CC
EE
EE
ICS9DB306
ICS9DB306
ICS9DB306
body package
body package
L Package
F Package
Top View
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DATA SHEET
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
PCIEXC0
PCIEXT0
FS0
nCLK
CLK
PLL_BW
V
V
BYPASS
FS1
PCIEXT5
PCIEXC5
V
CC
CCA
EE
CC

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ICS9DB306BLILFT Summary of contents

Page 1

PCI Express Jitter Attenuator G D ENERAL ESCRIPTION The ICS9DB306 is a high performance 1-to Differential-to-LVPECL Jitter Attenuator designed for HiPerClockS™ use in PCI Express™ systems. In some PCI Express systems, such as those found in desktop PCs, ...

Page 2

ICS9DB306 Data Sheet ABLE IN ESCRIPTIONS ...

Page 3

ICS9DB306 Data Sheet BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, T STG T 4A ABLE OWER UPPLY ...

Page 4

ICS9DB306 Data Sheet T 4D. LVPECL DC C ABLE HARACTERISTICS ...

Page 5

ICS9DB306 Data Sheet 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k The illustrated phase noise plot was taken using a low phase noise signal generator, the noise ...

Page 6

ICS9DB306 Data Sheet P ARAMETER CCA LVPECL V EE -1.3V ± 0.33V 3.3V LVPECL UTPUT OAD PCIEXC0:5x PCIEXT0:5x PCIEXC0:5y PCIEXT0:5y tsk( UTPUT KEW PCIEXC0:5 80% 20% PCIEXT0:5 t ...

Page 7

ICS9DB306 Data Sheet OWER UPPLY ILTERING ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor- mance, power supply isolation is required. The ICS9DB306 ...

Page 8

ICS9DB306 Data Sheet IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING and V input requirements. Figures show interface CMR examples for ...

Page 9

ICS9DB306 Data Sheet T LVPECL O ERMINATION FOR UTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs ...

Page 10

ICS9DB306 Data Sheet S E CHEMATIC XAMPLE Figure 5 shows an example of ICS9DB306 application schematic. In this example, the device is operated at V The decoupling capacitor should be located as close as possible to the power pin. The ...

Page 11

ICS9DB306 Data Sheet This section provides information on power dissipation and junction temperature for the ICS9DB306. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS9DB306 is the sum of the core power ...

Page 12

ICS9DB306 Data Sheet 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure calculate worst case power dissipation into ...

Page 13

ICS9DB306 Data Sheet T 7A ABLE VS IR LOW ABLE JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second ...

Page 14

ICS9DB306 Data Sheet ACKAGE UTLINE UFFIX FOR T 8A ABLE ACKAGE IMENSIONS ...

Page 15

ICS9DB306 Data Sheet ABLE RDERING NFORMATION ...

Page 16

ICS9DB306 Data Sheet ...

Page 17

ICS9DB306 Data Sheet www.IDT.com 6024 Silver Creek Valley Road Sales San Jose, CA 95138 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or ...

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