IDT5V9910A-7SOGI8 IDT, Integrated Device Technology Inc, IDT5V9910A-7SOGI8 Datasheet

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IDT5V9910A-7SOGI8

Manufacturer Part Number
IDT5V9910A-7SOGI8
Description
IC BUFFER ZD PLL SGL I/O 24-SOIC
Manufacturer
IDT, Integrated Device Technology Inc
Series
TurboClock™ JRr
Type
PLL Clock Driverr
Datasheet

Specifications of IDT5V9910A-7SOGI8

Pll
Yes with Bypass
Input
LVTTL
Output
LVTTL
Number Of Circuits
1
Ratio - Input:output
1:8
Differential - Input:output
No/No
Frequency - Max
85MHz
Divider/multiplier
No/No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Frequency-max
85MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
5V9910A-7SOGI8
FEATURES:
• Eight zero delay outputs
• <250ps of output to output skew
• Selectable positive or negative edge synchronization
• Synchronous output enable
• Output frequency: 15MHz to 85MHz
• 3 skew grades:
• 3-level inputs for PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• Low Jitter: <200ps peak-to-peak
• Available in SOIC package
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5V9910A
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
c
IDT5V9910A-2: t
IDT5V9910A-5: t
IDT5V9910A-7: t
2001
Integrated Device Technology, Inc.
SKEW0
SKEW0
SKEW0
<250ps
<500ps
<750ps
REF
FB
FS
3.3V LOW SKEW
PLL CLOCK DRIVER
TURBOCLOCK™ JR.
V
CCQ
PLL
/PE
1
GND/sOE
DESCRIPTION:
intended for high performance computing and data-communications appli-
cations. It has eight zero delay LVTTL outputs.
enabled. However, if GND/sOE is held high, all the outputs except Q
Q
synchronized with the positive edge of the REF clock input. When V
PE is held low, all the outputs are synchronized with the negative edge of
REF.
in order to drive the VCO. Phase differences cause the VCO of the PLL to
adjust upwards or downwards accordingly.
detector. The loop filter transfer function has been chosen to provide minimal
jitter (or frequency variation) while still providing accurate responses to input
frequency changes.
3
The IDT5V9910A is a high fanout phase locked-loop clock driver
When the GND/sOE pin is held low, all the outputs are synchronously
Furthermore, when the V
The FB signal is compared with the input REF signal at the phase detector
An internal loop filter moderates the response of the VCO to the phase
are synchronously disabled.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Q
Q
Q
Q
Q
Q
Q
Q
CCQ
0
1
2
3
4
5
6
7
/PE is held high, all the outputs are
SEPTEMBER 2001
IDT5V9910A
DSC 5847/3
2
CCQ
and
/

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IDT5V9910A-7SOGI8 Summary of contents

Page 1

... PLL CLOCK DRIVER TURBOCLOCK™ JR. DESCRIPTION: The IDT5V9910A is a high fanout phase locked-loop clock driver intended for high performance computing and data-communications appli- cations. It has eight zero delay LVTTL outputs. When the GND/sOE pin is held low, all the outputs are synchronously enabled ...

Page 2

... IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. PIN CONFIGURATION /PE 5 CCQ SOIC TOP VIEW PIN DESCRIPTION Pin Name Type Description REF I N Reference Clock Input Feedback Input (1) TEST I N When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation. ...

Page 3

... CC I Dynamic Power Supply Current per Output CCD I Total Power Supply Current TOT NOTE: 1. For eight outputs, each loaded with 20pF. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT5V9910A-5, -7 (Industrial) Min. Max. 3 3.6 -40 +85 Conditions Guaranteed Logic HIGH (REF, FB Inputs Only) Guaranteed Logic LOW (REF, FB Inputs Only) ...

Page 4

... Skew is the time between the earliest and the latest output transition among all outputs with the specified load the skew between all outlets. See AC TEST LOADS. SKEW 4. For IDT5V9910A measured with C SKEW0 the output-to-output skew between any two devices operating under the same conditions (V DEV 6 ...

Page 5

... IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. AC TEST LOADS AND WAVEFORMS Ω 150 Output Ω 150 Test Load AC TIMING DIAGRAM REF OTHER Q NOTES: Skew: The time between the earliest and the latest output transition among all outputs when all are loaded with 20pF and terminated with 75Ω ...

Page 6

... IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. ORDERING INFORMATION XX IDT XXXXX X Device Type Package Process CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Commercial (0°C to +70°C) Blank Industrial (-40°C to +85°C) I Small Outline IC (300-mil) ...

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