MC88915FN70 IDT, Integrated Device Technology Inc, MC88915FN70 Datasheet
MC88915FN70
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MC88915FN70 Summary of contents
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Low Skew CMOS PLL Clock Drivers The MC88915 Clock Driver utilizes phase-locked loop technology to lock its low skew outputs' frequency and phase onto an input reference clock designed to provide clock distribution for high performance PC's and ...
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MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS FEEDBACK REF_SEL Table 1. Pin Summary Pin Name Number SYNC[0] 1 SYNC[1] 1 REF_SEL 1 FREQ_SEL 1 FEEDBACK 1 RC1 1 Q(0– 2x_Q 1 Q/2 1 LOCK 1 RST 1 ...
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MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS FEEDBACK SYNC ( SYNC (1) 1 REF_SEL PLL_EN RST IDT™ / ICS™ CMOS PLL CLOCK DRIVERS PHASE/FREQ CHARGE PUMP/LOOP DETECTOR FILTER EXTERNAL REC NETWORK 0 1 MUX (÷1) 1 ...
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... CC 15 mW/Output 120 mW/Device T = 25°C 37.5 mW/Output 300 mW/Device T = 25°C Minimum Maximum — 3.0 (1) FN70 200 36 28.5 50% ± 25% = 5.0 pF) L Guaranteed Minimum MC88915FN55 MC88915FN70 55 70 27.5 35 MC88915 REV 6 JULY 10, 2007 Unit µ 5.0 V Unit ns ns Unit MHz MHz ...
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MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS Table 6. AC Electrical Characteristics (T Symbol Rise and Fall Times, all Outputs Into a 50 pF, 500 Ω Load (Between RISE FALL 0.2 V and 0.8 V (Outputs) CC ...
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MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS GENERAL AC SPECIFICATION NOTES 1. Statistical characterization techniques were used to guarantee those specifications which cannot be measured on the ATE. MC88915 units were fabricated with key transistor properties intentionally varied to create ...
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MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS RC1 EXTERNAL LOOP FILTER 330 Ω R2 0.1 µF C1 With the 470 kΩ resistor tied in this fashion, the t specification measured at the input pins is 2.25 ns ± ...
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MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS –0.50 –0.75 –1.00 –1.25 –1.50 2.5 5.0 7.5 10.0 SYNC INPUT FREQUENCY (MHz) Figure 5a t versus Frequency Variation for Q/2 Output Fed PD Back, Including Process and Voltage Variation @ 25°C (with ...
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MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS SYNC INPUT (SYNC[1] OR SYNC[0]) FEEDBACK INPUT Q/2 OUTPUT t SKEWALL Q0–Q4 OUTPUTS Q5 OUTPUT 2X_Q OUTPUT Figure 6. Output/Input Switching Waveforms and Timing Diagrams (These waveforms represent the hook-up configuration of TIMING ...
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MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS 12.5 MHz FEEDBACK SIGNAL HIGH RST Q5 FEEDBACK LOW REF_SEL CRYSTAL 12.5 MHz INPUT SYNC[0] OSCILLATOR ANALOG V CC EXTERNAL LOOP RC1 FILTER ANALOG GND FQ_SEL Q0 HIGH Figure 7a. Wiring Diagram and ...
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MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS 0.1 µF HIGH 10 µF LOW FREQUENCY FREQUENCY BYPASS BYPASS Figure 8. Recommended Loop Filter and Analog Isolation Scheme for the MC88915 NOTES CONCERNING LOOP FILTER AND BOARD LAYOUT ISSUES 1. Figure 8 ...
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MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS CLOCK SYSTEM CLOCK SOURCE DISTRIBUTE CLOCK @ f CLOCK @ 2f AT POINT OF USE Figure 9. Representation of a Potential Multi-Processing Application Utilizing the MC88915 for Frequency Multiplication and Low Board-to-Board Skew ...
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MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS IDT™ / ICS™ CMOS PLL CLOCK DRIVERS PACKAGE DIMENSIONS PACKAGE DIMENSIONS CASE 776-02 ISSUE D PLCC PLASTIC PACKAGE 13 MC88915 REV 6 JULY 10, 2007 ...
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MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 netcom@idt.com 408-284-8200 480-763-2056 Fax: 408-284-2775 Corporate Headquarters Asia Pacific and Japan Integrated Device Technology, Inc. Integrated Device ...