ICS813323BGLFT IDT, Integrated Device Technology Inc, ICS813323BGLFT Datasheet
ICS813323BGLFT
Specifications of ICS813323BGLFT
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ICS813323BGLFT Summary of contents
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VCXO Jitter Attenuator & FemtoClock General Description The ICS813323 is a PLL based synchronous multiplier ICS that is optimized for SONET clock jitter attenuation and frequency translation. The device contains two internal HiPerClockS™ frequency multiplication stages which are cascaded in ...
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ICS813323 Data Sheet Table 1. Pin Descriptions Number Name Analog 1 LF Input/Output 2 V Power CCA 3 V Power Power CCO 5, 6 nQ0, Q0 19, 20 Q1, nQ1 Output 21, 22 Q2, nQ2 7, ...
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ICS813323 Data Sheet Table 3C. OE Function Table Input Clock Outputs OE Q[0:2] nQ[0:2] 0 LOW HIGH 1 Enabled Enabled Table 3D. Bypass Function Table nBypass Input Operation 0 VCXO jitter attenuation PLL and FemtoClock multiplier bypassed. Input passed directly ...
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ICS813323 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those ...
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ICS813323 Data Sheet Table 4D. Differential DC Characteristics, V Symbol Parameter I Input High Current IH I Input Low Current IL V Peak-to-Peak Input Voltage PP V Common Mode Input Voltage; NOTE 1 CMR NOTE 1. Common mode voltage is ...
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ICS813323 Data Sheet AC Electrical Characteristics Table 5A. AC Characteristics, V Symbol Parameter f Input Frequency IN f Output Frequency OUT RMS Phase Jitter, (Random), tjit(Ø) NOTE 1 tjit(per) Period Jitter, RMS; NOTE 2 tsk(o) Output Skew; NOTE 3, 4 ...
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ICS813323 Data Sheet Table 5B. AC Characteristics, V Symbol Parameter f Input Frequency IN f Output Frequency OUT RMS Phase Jitter, (Random), tjit(Ø) NOTE 1 tjit(per) Period Jitter, RMS; NOTE 2 tsk(o) Output Skew; NOTE ...
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ICS813323 Data Sheet Typical Phase Noise at 155.52MHz @ 3.3V ICS813323BG REVISION A APRIL 13, 2010 VCXO JITTER ATTENUATOR & FEMTOCLOCK Offset Frequency (Hz) 8 MULTIPLIER ™ ©2010 Integrated Device Technology, Inc. ...
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ICS813323 Data Sheet Typical Phase Noise at 155.52MHz @ 3.3V Core/2.5V Output ICS813323BG REVISION A APRIL 13, 2010 VCXO JITTER ATTENUATOR & FEMTOCLOCK Offset Frequency (Hz) 9 MULTIPLIER ™ ©2010 Integrated Device Technology, Inc. ...
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ICS813323 Data Sheet Parameter Measurement Information CC, V CCO V CCA LVPECL V EE -1.3V ± 0.165V 3.3V Core/3.3V LVPECL Output Load AC Test Circuit V CC nCLK V Cross Points PP CLK V EE Differential Input ...
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ICS813323 Data Sheet Parameter Measurement Information, continued VCXO & FemtoClock PLL Lock Time Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, ...
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ICS813323 Data Sheet Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage V REF the bias resistors R1 and R2. The bypass capacitor ...
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ICS813323 Data Sheet Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING and V input requirements. Figures show interface CMR examples for the CLK/nCLK input driven ...
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ICS813323 Data Sheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that ...
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ICS813323 Data Sheet Termination for 2.5V LVPECL Outputs Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω – 2V. For V = 2.5V, the V CC CCO ...
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ICS813323 Data Sheet Schematic Example Figure 6 shows an example of the ICS813323 application schematic. In this example, the device is operated at V decoupling capacitors should be located as close as possible to the power pin. The input is ...
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ICS813323 Data Sheet VCXO-PLL E C XTERNAL OMPONENTS Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be ...
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ICS813323 Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS813323. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS813323 is the sum of the ...
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ICS813323 Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. LVPECL output driver circuit and termination are shown in Figure 6. V CCO Q1 Figure 6. LVPECL ...
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ICS813323 Data Sheet Reliability Information θ Table 7. vs. Air Flow Table for a 24 Lead TSSOP JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS813323 is: 2915 Package Outline and Package ...
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ICS813323 Data Sheet Ordering Information Table 9. Ordering Information Part/Order Number Marking 813323BGLF ICS813323BGLF 813323BGLFT ICS813323BGLF NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information ...
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ICS813323 Data Sheet 6024 Silver Creek Valley Road Sales 800-345-7015 (inside USA) San Jose, California 95138 +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications ...