ICS810251AGILF IDT, Integrated Device Technology Inc, ICS810251AGILF Datasheet - Page 4

• Manufacturer Part Number: ICS810251AGILF
• Description: IC VCXO SYNC ETH ATTEN 16-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Jitter Attenuator, Voltage Controlled Crystal Oscillator (VCXO)r

Specifications of ICS810251AGILF

• Pll: Yes with Bypass
• Input: Clock
• Output: LVCMOS, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/No
• Frequency - Max: 25MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 25MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 810251AGILF

ICS810251I Data Sheet
Table 3C. LVCMOS/LVTTL DC Characteristics, V
NOTE 1: Outputs terminated with 50
AC Electrical Characteristics
Table 4A. AC Characteristics, V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized using a 616Hz bandwidth filter.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Please refer to the Phase Noise Plot.
ICS810251AGI REVISION A JULY 28, 2009
Symbol
V
V
I
I
V
V
Symbol
f
f
f
t
tjit(θ)
t
t
odc
IH
IL
REF
VCO
OUT
JIT(CC)
JIT(PER)
R
OH
OL
IH
IL
/ t
F
Parameter
Input
High Voltage
Input
Low Voltage
Input
High Current
Input
Low Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Parameter
Input Reference Frequency
VCXO-PLL Frequency
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
RMS Phase Jitter (Random);
NOTE 2
Period jitter
Output Rise/Fall Time
Output Duty Cycle
CLK_IN
OE, PLL_SEL
CLK_IN
OE, PLL_SEL
Ω
DD
to V
= V
DDO
DDO
/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
f
= 3.3V ± 5%, T
OUT
V
V
DD
DD
V
V
= 25MHz, Integration Range:
DD
DD
DD
= 3.465V or 2.625V, V
= 3.465V or 2.625V, V
Test Conditions
= V
= V
1kHz – 1MHz
V
V
V
V
20% to 80%
= V
Test Conditions
DDO
DDO
DDO
DDO
V
V
V
V
IN
IN
DD
DD
DD
DD
DDO
= 3.465V or 2.625V
= 3.465V or 2.625V
= 3.3V ± 5%
= 2.5V ± 5%
= 3.3V ± 5%
= 2.5V ± 5%
A
= 3.465V
= 2.625V
= 3.465V
= 2.625V
= -40°C to 85°C
= 3.3V ± 5% or 2.5V ± 5%, T
4
IN
IN
= 0V
= 0V
VCXO AND SYNCHRONOUS ETHERNET JITTER ATTENUATOR
Minimum
500
Minimum
48
-150
-0.3
-0.3
1.7
2.6
1.8
-5
2
A
= -40°C to 85°C
Typical
©2009 Integrated Device Technology, Inc.
0.22
Typical
125
25
25
25
Maximum
Maximum
V
V
DD
DD
1200
45
52
150
0.8
0.7
0.6
0.5
5
5
+ 0.3
+ 0.3
Units
Units
MHz
MHz
MHz
MHz
µA
µA
µA
µA
ps
ps
ps
ps
%
V
V
V
V
V
V
V
V