SI5325B-C-GM Silicon Laboratories Inc, SI5325B-C-GM Datasheet
SI5325B-C-GM
Specifications of SI5325B-C-GM
Related parts for SI5325B-C-GM
SI5325B-C-GM Summary of contents
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ROGRAMMABLE Description The Si5325 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5325 accepts dual clock inputs ranging from 10 to 710 MHz and generates two clock outputs ...
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Si5325 2 Preliminary Rev. 0.4 ...
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T C ABLE O F ONTENTS Section 1. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si5325 Table 1. Performance Specifications (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Temperature Range T A Supply Voltage V DD Supply Current I DD Input Clock Frequency CK F (CKIN1, CKIN2) Output Clock ...
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Table 1. Performance Specifications (Continued 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol PLL Performance Jitter Generation J GEN Jitter Transfer J PK Phase Noise CKO PN Subharmonic Noise SP SUBH Spurious Noise SP ...
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Si5325 622 MHz In, 622 MHz Out BW=877 kHz -50 -70 -90 -110 -130 -150 -170 1000 10000 OC-48, 12 kHz to 20 MHz OC-192, 20 kHz to 80 MHz OC-192, 4 MHz to 80 MHz OC-192, 50 kHz to ...
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C 4 System C 3 Power Ferrite Supply Bead 3 130 130 CKIN1+ CKIN1– 82 82 Input Clock Sources* 130 130 ...
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Si5325 1. Functional Description The Si5325 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5325 accepts dual clock inputs ranging from 10 to 710 MHz and generates two synchronous clock outputs ranging ...
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Pin Descriptions: Si5325 Pin numbers are preliminary and subject to change. Pin # Pin Name I/O 1 RST 14, NC 18, 30 INT_C1B O Note: Internal register names are indicated by underlined italics, ...
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Si5325 Table 3. Si5325 Pin Descriptions (Continued) Pin # Pin Name I/O 4 C2B O 5, 10 19, GND GND CKIN2 CKIN2– 16 CKIN1 ...
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Table 3. Si5325 Pin Descriptions (Continued) Pin # Pin Name I/O 22 SCL I 23 SDA_SDO I A2_SS 27 SDI I 29 CKOUT1– CKOUT1+ 34 CKOUT2– CKOUT2+ 36 CMODE ...
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Si5325 3. Register Map All register bits that are not defined in this map should always be written with the specified Reset Values. The writing to these bits of values other than the specified Reset Values may result in undefined ...
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Register 128 129 130 CLAT- DIGHOLD- PROGRESS VALID 131 132 134 135 PARTNUM_RO[3:0] 136 RST_REG ICAL 138 139 142 143 185 N2_LS[15:8] N2_LS[7:0] N31[15:8] N31[7:0] ...
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Si5325 4. Register Descriptions Register 0. Bit D7 D6 Reserved Reserved Name R R Type Reset value = 0001 0100 Bit Name 7:6 Reserved Reserved. 5 CKOUT_ CKOUT Always On. ALWAYS_ON This will bypass the SQ_ICAL function. Output will be ...
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Register 1. Bit D7 D6 Reserved Name R Type Reset value = 1110 0100 Bit Name 7:4 Reserved Reserved. 3:2 CK_PRIOR2 CK_PRIOR 2. [1:0] Selects which of the input clocks will be 2nd priority in the autoselection state machine. 00: ...
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Si5325 Register 3. Bit D7 D6 CKSEL_REG [1:0] Name R/W Type Reset value = 0000 0101 Bit Name 7:6 CKSEL_REG CKSEL_REG. [1:0] If the device is operating in register-based manual clock selection mode (AUTOSEL_REG = 00), and CKSEL_PIN = 0, ...
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Register 4. Bit D7 D6 AUTOSEL_REG [1:0] Name R/W Type Reset value = 0001 0010 Bit Name 7:6 AUTOSEL_ AUTOSEL_REG [1:0] REG [1:0] Selects method of input clock selection to be used. 00: Manual (either register or pin controlled, see ...
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Si5325 Register 6. Bit D7 D6 Reserved SLEEP Name R R/W Type Reset value = 0010 1101 Bit Name 7 Reserved Reserved. 6 SLEEP SLEEP. In sleep mode, all clock outputs are disabled and the maximum amount of internal cir- ...
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Register 7. Bit D7 D6 Name Type Reset value = 0010 1010 Bit Name 7:3 Reserved. Reserved. 2:0 FOSREFSEL FOSREFSEL [2:0]. [2:0] Selects which input clock is used as the reference frequency for Frequency Off-Set (FOS) alarms. 000: XA/XB (External ...
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Si5325 Register 8. Bit D7 D6 HLOG_2[1:0] Name R/W Type Reset value = 0000 0000 Bit Name 7:6 HLOG_2 [1:0] HLOG_2 [1:0]. 00: Normal operation 01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will ...
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Register 10. Bit D7 D6 Reserved Name R Type Reset value = 0000 0000 Bit Name 7:4 Reserved Reserved. 3 DSBL2_REG DSBL2_REG. This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is selected, the NC2 output ...
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Si5325 Register 19. Bit D7 D6 FOS_EN FOS_THR [1:0] Name R/W R/W Type Reset value = 0010 1100 Bit Name 7:5 FOS_EN FOS_EN. Frequency Offset Enable globally disables FOS. See the individual FOS enables (FOSX_EN, register 139). 0: FOS disable ...
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Register 20. Bit D7 D6 Reserved Name R Type Reset value = 0011 1110 Bit Name 7:4 Reserved Reserved. 3 CK2_BAD_ CK2_BAD_PIN. PIN The CK2_BAD status can be reflected on the C2B output pin. 0: C2B output pin tristated 1: ...
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Si5325 Register 21. Bit D7 D6 Reserved Name R Force 1 Type Reset value = 1111 1111 Bit Name 7:2 Reserved Reserved. 1 CK1_ACTV_PIN CK1_ACTV_PIN. The CK1_ACTV_REG status bit can be reflected to the CS_CA output pin using the CK1_ACTV_PIN ...
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Register 22. Bit Reserved Name R Type Reset value = 1101 1111 Bit Name 7:4 Reserved Reserved. 3 CK_ACTV_ POL CK_ACTV_POL. Sets the active polarity for the CS_CA signals when reflected on an output pin. 0: Active ...
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Si5325 Register 23. Bit D7 D6 Reserved Name Type Reset value = 0001 1111 Bit Name 7:3 Reserved Reserved. 2 LOS2_MSK LOS2_MSK. Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt. Writes to this ...
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Register 24. Bit D7 D6 Reserved Name Type Reset value = 0011 1111 Bit Name 7:3 Reserved Reserved. 2 FOS2_MSK FOS2_MSK. Determines if the FOS2_FLG is used to in the generation of an interrupt. Writes to this register do not ...
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Si5325 Register 25. Bit D7 D6 N1_HS [2:0] Name R/W Type Reset value = 0010 0000 Bit Name 7:5 N1_HS [2:0] N1_HS [2:0]. Sets value for N1 high speed divider which drives NCn_LS ( low-speed divider. ...
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Register 32. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 NC1_LS NC1_LS [15:8]. [15:8] Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must odd. 00000000000000000000 = 1 00000000000000000001 = 2 ...
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Si5325 Register 34. Bit D7 D6 Reserved Name R Type Reset value = 0000 0000 Bit Name 7:4 Reserved Reserved. 3:0 NC2_LS NC2_LS [19:16]. [19:16] Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must odd. ...
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Register 36. Bit D7 D6 Name Type Reset value = 0011 0001 Bit Name 7:0 NC2_LS [7:0] NC2_LS [7:0]. Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must odd. 00000000000000000000 = 1 00000000000000000001 = 2 ...
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Si5325 Register 41. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 N2_LS [15:8] N2_LS [15:8]. Sets the value for the N2 low-speed divider, which drives the phase detector. Must be an even number ranging from ...
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Register 43. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:3 Reserved Reserved. 2:0 N31 [18:16] N31 [18:16]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 ...
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Si5325 Register 45. Bit D7 D6 Name Type Reset value = 0000 1001 Bit Name 7:0 N31_[7:0 N31_[7:0]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 Valid divider ...
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Register 47. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 N32_[15:8] N32_[15:8]. Sets value for input divider for CKIN2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 Valid divider values=[1, ...
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Si5325 Register 55h. Bit D7 D6 Reserved Name R Type Reset value = 0000 0000 Bit Name 7:6 Reserved Reserved. 5:3 CLKIN2RATE[2:0] CLKIN2RATE[2:0]. CKINn frequency selection for FOS alarm monitoring. 000 MHz 001 MHz ...
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Register 128. Bit Name Type Reset value = 0010 0000 Bit Name 7:2 Reserved Reserved. 1 CK2_ACTV_REG CK2_ACTV_REG. Indicates if CKIN2 is currently the active clock for the PLL input. 0: CKIN2 is not the active input ...
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Si5325 Register 130. Bit D7 D6 CLATPROGRESS Name R Type Reset value = 0000 0001 Bit Name 7 CLAT- CLAT Progress. PROGRESS Indicates if the last change in the CLAT register has been processed. 0: Coarse skew adjustment not in ...
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Register 131. Bit D7 D6 Name Type Reset value = 0001 1111 Bit Name 7:3 Reserved Reserved. 2 LOS2_FLG CKIN2 Loss-of-Signal Flag. 0: Normal operation. 1: Held version of LOS2_INT. Generates active output interrupt if output interrupt pin is enabled ...
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Si5325 Register 132. Bit D7 D6 Reserved Name R Type Reset value = 0000 0010 Bit Name 7:4, 0 Reserved Reserved. 3 FOS2_FLG CLKIN_2 Frequency Offset Flag. 0: Normal operation. 1: Held version of FOS2_INT. Generates active output interrupt if ...
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Register 134. Bit D7 D6 Name Type Reset value = 0000 0001 Bit Name 7:0 PARTNUM_ Device 2). RO [11:0] 0000 0001 1001: Si5325 Register 135. Bit D7 D6 PARTNUM_RO [3:0] Name R Type Reset value = ...
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Si5325 Register 136. Bit D7 D6 Name RST_REG ICAL R/W R/W Type Reset value = 0000 0000 Bit Name 7 RST_REG Internal Reset (Same as Pin Reset). Note: The I2C (or SPI) port may not be accessed until 10 ms ...
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Register 138. Bit D7 D6 Name Type Reset value = 0000 1111 Bit Name 7:2 Reserved Reserved. 1 LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2). Note: LOS2_EN is split between two registers. 00: Disable ...
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Si5325 Register 139. Bit D7 D6 Reserved LOS2_EN [0:0] LOS1_EN [0:0] Name R Type Reset value = 1111 1111 Bit Name 7:6, Reserved Reserved. 3:2 5 LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2). Note: ...
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Register 142. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 INDEPENDENTSKEW1 [7:0] INDEPENDENTSKEW1. Register 143. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 INDEPEND-ENTSKEW2 [7:0] Register 185. Bit D7 D6 ...
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Si5325 Table 4. CKOUT_ALWAYS_ON and SQICAL Truth Table CKOUT_ALWAYS_ON SQICAL Table 5 lists all of the register locations that should be followed by an ICAL after their contents are changed. Table 5. ...
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... Ordering Guide Ordering Part Output Clock Number Frequency Range Si5325A-C-GM 10–945 MHz 970–1134 MHz 1.213–1.417 GHz Si5325B-C-GM 10–808 MHz Si5325C-C-GM 10–346 MHz Package ROHS6, Pb-Free 36-Lead QFN Yes 36-Lead QFN Yes 36-Lead QFN Yes Preliminary Rev. 0.4 Si5325 Temperature Range – ...
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Si5325 6. Package Outline: 36-Pin QFN Figure 4 illustrates the package details for the Si5325. Table 6 lists the values for the dimensions shown in the illustration. Figure 4. 36-Pin Quad Flat No-lead (QFN) Symbol Millimeters Min A 0.80 A1 ...
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Recommended PCB Layout Table 7. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is ...
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Si5325 8. Top Mark Laser Mark Method: 0.80 mm Font Size: Right-Justified Si5325Q Line 1 Marking: C-GM Line 2 Marking: YYWWRF Line 3 Marking: Pin 1 Identifier Line 4 Marking: XXXX 50 Customer Part Number Q = Speed Code: A, ...
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Si5325 OCUMENT HANGE IST Revision 0.23 to Revision 0.24 Clarified that the two outputs have a common, higher frequency source on page 1. Changed LVTTL to LVCMOS in Table 2, “Absolute Maximum Ratings,” on page ...
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