DS1087LU-2CL+T Maxim Integrated Products, DS1087LU-2CL+T Datasheet - Page 5

• Manufacturer Part Number: DS1087LU-2CL+T
• Description: IC ECONOSCILLATOR SS 3.6V 8-MSOP
• Manufacturer: Maxim Integrated Products
• Series: EconOscillator™r
• Type: Clock Generatorr

Specifications of DS1087LU-2CL+T

• Pll: No
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: No/No
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency-max: -

(V
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
CC
7.5
7.0
6.5
6.0
5.5
5.0
= 3.3V, T
-40
-30
V
FREQUENCY = 66.6MHz
OE = PDN = V
CC
-20
All voltages are referenced to ground.
This is the absolute accuracy of the master oscillator frequency at the default settings.
This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at
T
This is the percentage frequency change from the +25°C frequency due to temperature at V
The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency.
This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally
introduced to allow the oscillator to stabilize. t
on the programmed master oscillator frequency.
Output voltage swings may be impaired at high frequencies combined with high output loading.
A fast-mode device can be used in a standard-mode system, but the requirement t
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line at least t
250ns = 1250ns before the SCL line is released.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
nal) to bridge the undefined region of the falling edge of SCL.
The maximum t
C
Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr
+125°C bake, 168hr 85°C/85%RH moisture soak, and 3 solder reflow passes +240 +0/-5°C peak) followed by 1000hr
max V
Autoclave.
= 3.3V
A
ACTIVE SUPPLY CURRENT
B
-10
—total capacitance of one bus line, timing referenced to 0.9 x V
= +25°C.
vs. TEMPERATURE
A
0
TEMPERATURE (°C)
CC
CC
= +25°C, unless otherwise noted.)
10
biased 125°C HTOL, 1000 temperature cycles at -55°C to +125°C, and 168hr 121°C/2 ATM Steam/Unbiased
20
8.2pF LOAD
30
HD:DAT
40
15pF LOAD
3.3V Spread-Spectrum EconOscillator
50
4.7pF LOAD
UNLOADED
60
need only be met if the device does not stretch the LOW period (t
70
80
90
_____________________________________________________________________
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
2.7
FREQUENCY = 66.6MHz
OUTPUT UNLOADED
OE = PDN = V
2.8 2.9 3.0
stab
ACTIVE SUPPLY CURRENT
is equivalent to approximately 512 master clock cycles and depends
CC
vs. VOLTAGE
VOLTAGE (V)
3.1
3.2
Typical Operating Characteristics
3.3
3.4
CC
3.5
and 0.1 x V
3.6
CC
SU:DAT
7
6
5
4
3
2
1
0
.
1
OUTPUT UNLOADED
LOW
SUPPLY CURRENT vs. PRESCALER
R MAX
> 250ns must then be met. This
) of the SCL signal.
CC
PRESCALER (DECIMAL)
= 3.3V.
+ t
10
SU:DAT
IH MIN
= 1000ns +
of the SCL sig-
100
3.6V
3.3V
2.7V
1000
5