DS1087LU-2CL+T Maxim Integrated Products, DS1087LU-2CL+T Datasheet - Page 8

• Manufacturer Part Number: DS1087LU-2CL+T
• Description: IC ECONOSCILLATOR SS 3.6V 8-MSOP
• Manufacturer: Maxim Integrated Products
• Series: EconOscillator™r
• Type: Clock Generatorr

Specifications of DS1087LU-2CL+T

• Pll: No
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: No/No
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency-max: -

A block diagram of the DS1087L is shown in
The internal master oscillator can generate a square
wave with a frequency range of 33.3MHz to 66.6MHz.
The master oscillator frequency and output frequency
are factory programmed, although the user can use the
programmable divider to divide the master oscillator
frequency by 2
Two user control signals control the output. The output-
enable pin, OE, gates the clock output buffer and the
PDN pin disables the master oscillator and turns off the
output for power-sensitive applications (note: the
power-down command must persist for at least two out-
put frequency cycles plus 10µs for deglitching purpos-
es). On power-up, the output is disabled until power is
stable and the master oscillator has generated 512
clock cycles.
Both controls feature a synchronous enable, which
ensures there are no output glitches when the output is
enabled. The synchronous enable also ensures a con-
stant time interval (for a given frequency setting) from
an enable signal to the first output transition.
The DS1087L can reduce radiated emission peaks. The
output frequency can be dithered 2% or 4% below the
3.3V Spread-Spectrum EconOscillator
Table
X
Figure 2. Output Frequency vs. Dither Rate
8
REGISTER
PRESCALER
ADDR
WRITE EE
OUTPUT FREQUENCY
1
= Don’t care; read as one.
_____________________________________________________________________
(f
O
1. Register Summary
/N) - 4%
f
O
/N
WHERE N = (2
f
0
0
Output Control and Power-Down
= FACTORY PROGRAMMED MASTER OSCILLATOR FREQUENCY
ADDR
x
0Dh
02h
3Fh
(where x equals 0 to 8).
X
)
Detailed Description
X
X
1
1
f
O
/4096
X
X
1
1
Output Frequency
Spread Spectrum
LO/
HIZ
X
1
J0
X
BINARY
No Data
1
2f
Figure
O
/4096
WC
P3
DITHER RATE
1.
A2
P2
P1
A1
programmed frequency. Although the output frequency
changes when the dither is enabled, the duty cycle
does not change.
The dither is controlled by the J0 bit in the PRESCALER
register and enabled with the SPRD pin. The maximum
spectral attenuation occurs when the prescaler is set to
1. The spectral attenuation is reduced by 2.7dB for
every factor of 2 that is used in the prescaler. This hap-
pens because the prescaler’s divider function tends to
average the dither in creating the lower frequency.
However, the most stringent spectral emission limits are
imposed on the higher frequencies where the prescaler
is set to a low divider ratio.
A triangle-wave generator injects an offset element into
the master oscillator to dither its output. The dither rate
(see Equation 1) is based on the master oscillator fre-
quency.
versus dither rate.
where f
The DS1087L registers are used to change the dither
amount, output frequency, and slave address. A sum-
mary of the registers is shown in
grammed into EEPROM, the settings only need to be
reprogrammed if it is desired to reconfigure the device.
PRESCALER Register
Bit 5:
Bit 4:
A0
P0
0
Dither Rate
Figure
= master oscillator frequency
FACTORY DEFAULT
Output Low or High-Z. The LO/HIZ bit
controls the output. During power-down,
while the output is deactivated, if the
LO/HIZ bit is set to 0, the output is high-Z.
If the LO/HIZ bit is set to 1, the output is
driven low.
Dither Control. The J0 bit controls the
dither applied to the output. When J0 is
high, 2% peak dither is selected. When
J0 is low, 4% peak dither is selected.
2 shows a plot of the output frequency
110- - - - - b
11110000b
—
=
4096
f
0
Register Summary
Table
ACCESS
1. Once pro-
R/W
R/W
—
(1)