SY100S834LZC Micrel Inc, SY100S834LZC Datasheet

SY100S834LZC

Manufacturer Part Number

SY100S834LZC

Description

IC CLOCK GEN 3.3V/5V 16-SOIC

Manufacturer

Micrel Inc

Series

Precision Edge®r

Type

Clock Generatorr

Datasheet

1.SY100S834ZG.pdf (6 pages)

Specifications of SY100S834LZC

Pll

Input

ECL, PECL

Output

Clock

Number Of Circuits

Ratio - Input:output

1:3

Differential - Input:output

Yes/Yes

Divider/multiplier

Yes/No

Voltage - Supply

3 V ~ 3.8 V

Operating Temperature

0°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

16-SOIC (3.9mm Width)

Function

Clock Generator

Package Type

SOIC

Pin Count

Mounting

Surface Mount

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Frequency-max

Lead Free Status / RoHS Status

Not Compliant, Contains lead / RoHS non-compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

SY100S834LZC

Manufacturer:

SYNERGY

Quantity:

20 000

Current page: 1 of 6
Download datasheet (78Kb)

Micrel, Inc.

Notes:

Z = LOW-to-HIGH transition

ZZ = HIGH-to-LOW transition

Precision Edge is a registered trademark of Micrel, Inc.

M9999-111009

hbwhelp@micrel.com or (408) 955-1690

FEATURES

TRUTH TABLE

PIN NAMES

3.3V (SY100S834L) and 5V (SY100S834) power

supply options

50ps output-to-output skew

Synchronous enable/disable

Master Reset for synchronization

Internal 75K

Available in 16-pin SOIC package

SEL

CLK

SEL

Divide by 2

Divide by 1

Outputs

Ω

input pull-down resistors

Differential Clock Inputs

Function Select

Synchronous Enable

Master Reset

Reference Output

Differential ÷1 or ÷2 Outputs

Differential ÷2 or ÷4 Outputs

Differential ÷4 or ÷8 Outputs

Divide by 4

Divide by 2

Outputs

Function

Divide

Hold Q

Reset Q

Function

Divide by 8

Divide by 4

0–2

Outputs

0–2

(

CLOCK GENERATION CHIP

4) OR (

÷4, ÷8) clock generation chip designed explicitly for low

skew clock generation applications. The internal dividers

are synchronous to each other, therefore, the common

output edges are all precisely aligned. The devices can

be driven by either a differential or single-ended ECL or,

if positive power supplies are used, PECL input signal.

In addition, by using the V

can be AC-coupled into the device. If a single-ended

input is to be used, the V

to the CLK input and bypassed to ground via a 0.01µF

capacitor. The V

switching reference for the input of the SY100S834/L

under single-ended input conditions. As a result, this pin

can only source/sink up to 0.5mA of current.

what clock generation chip function is. When FS

is LOW, SY100S834/L functions as a divide by 2, by 4

and by 8 clock generation chip. However, if FS

is HIGH, it functions as a divide by 1, by 2 and by 4

clock generation chip. This latter feature will increase

the clock frequency by two folds.

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the input clock, therefore,

all associated specification limits are referenced to the

negative edge of the clock input.

state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple SY100S834/Ls in a system.

DESCRIPTION

The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2,

The Function Select (F

The common enable (EN) is synchronous so that the

Upon start-up, the internal flip-flops will attain a random

output is designed to act as the

SEL

output should be connected

) input is used to determine

output, a sinusoidal source

Precision Edge

SY100S834L

Rev.: I

Issue Date: November 2009

Precision Edge

SY100S834

Precision Edge®

SY100S834L

SY100S834

Amendment: /0

input

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SY100S834LZC Summary of contents

Page 1

Micrel, Inc. FEATURES 3.3V (SY100S834L) and 5V (SY100S834) power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Ω Internal 75K input pull-down resistors Available in 16-pin SOIC package TRUTH TABLE CLK ...

Page 2

... Pb-Free package is recommended for new designs. 2 Precision Edge® SY100S834L Operating Package Range Marking Commercial SY100S834ZC Commercial SY100S834ZC Commercial SY100S834LZC Commercial SY100S834LZC Industrial SY100S834ZI Industrial SY100S834ZI Industrial SY100S834LZI Industrial SY100S834LZI Industrial SY100S834ZG with Pb-Free bar-line indicator Pb-Free Industrial SY100S834ZG with Pb-Free bar-line indicator Pb-Free ...

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SY100S834LZC Micrel Inc, SY100S834LZC Datasheet

SY100S834LZC

Specifications of SY100S834LZC

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SY100S834LZC Summary of contents

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