CY7B9920-5SI Cypress Semiconductor Corp, CY7B9920-5SI Datasheet

no-image

CY7B9920-5SI

Manufacturer Part Number
CY7B9920-5SI
Description
IC CLK BUFF SKEW 8OUT 24SOIC
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Distribution, Zero Delay Bufferr
Datasheet

Specifications of CY7B9920-5SI

Pll
Yes
Input
Clock
Output
CMOS
Number Of Circuits
1
Ratio - Input:output
1:8
Differential - Input:output
No/No
Frequency - Max
80MHz
Divider/multiplier
No/No
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Frequency-max
80MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7B9920-5SI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Low Skew Clock Buffer
Features
Functional Description
The CY7B9910 and CY7B9920 low skew clock buffers offer low
skew system clock distribution. These multiple output clock
drivers optimize the timing of high performance computer
systems. Each of the eight individual drivers can drive terminated
transmission lines with impedances as low as 50 . They deliver
minimal and specified output skews and full swing logic levels
(CY7B9910 TTL or CY7B9920 CMOS).
The completely integrated PLL enables ‘zero delay’ capability.
External divide capability, combined with the internal PLL, allows
distribution of a low frequency clock that is multiplied by virtually
any factor at the clock destination. This facility minimizes clock
distribution difficulty while allowing maximum system clock
speed and flexibility.
Cypress Semiconductor Corporation
Document Number: 38-07135 Rev. *G
Logic Block Diagram
All outputs skew < 100 ps typical (250 max)
15 to 80 MHz output operation
Zero input to output delay
50% duty cycle outputs
Outputs drive 50 terminated lines
Low operating current
24-pin small-outline integrated circuit (SOIC) package
Jitter: < 200 ps peak-to-peak, < 25 ps RMS
REF
FB
TEST
FS
Freq Det
Phase
198 Champion Court
Filter
Block Diagram Description
Phase Frequency Detector and Filter
The phase frequency detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the voltage controlled oscillator (VCO). These
blocks, along with the VCO, form a phase-locked loop (PLL) that
tracks the incoming REF signal.
VCO
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency. The operational range of the VCO is
determined by the FS control pin.
Controlled
Oscillator
Voltage
San Jose
Low Skew Clock Buffer
,
Q6
Q5
Q0
Q1
Q2
Q3
Q4
Q7
CA 95134-1709
Revised October 7, 2010
CY7B9910
CY7B9920
408-943-2600
[+] Feedback

Related parts for CY7B9920-5SI

CY7B9920-5SI Summary of contents

Page 1

... Jitter: < 200 ps peak-to-peak, < RMS Functional Description The CY7B9910 and CY7B9920 low skew clock buffers offer low skew system clock distribution. These multiple output clock drivers optimize the timing of high performance computer systems. Each of the eight individual drivers can drive terminated transmission lines with impedances as low as 50  ...

Page 2

... Switching Characteristics ................................................ 6 Operational Mode Descriptions ...................................... 7 Ordering Information ........................................................ 8 Ordering Code Definition ............................................. 8 Document Number: 38-07135 Rev. *G Package Diagram .............................................................. 9 Acronyms ........................................................................ 10 Document Conventions ................................................. 10 Units of Measure ....................................................... 10 Document History Page ................................................. 11 Sales, Solutions, and Legal Information ...................... 12 Worldwide Sales and Design Support ....................... 12 Products .................................................................... 12 PSoC Solutions ......................................................... 12 CY7B9910 CY7B9920 Page [+] Feedback ...

Page 3

... Test Mode The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910 and CY7B9920 to operate as described in Block Diagram Description on page have a removable jumper to ground or be tied LOW through a 100  resistor. This enables an external tester to change the state of these pins ...

Page 4

... If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t CC all datasheet limits are achieved. 5. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B9920 outputs are not short circuit protected. Document Number: 38-07135 Rev. *G ...

Page 5

... V = 30pF for –5 and – 2 devices) 0.0 V 1 ns TTL Input Test Waveform (CY7B9910) 80 for –5 and –2 devices 20% 0.0 V 3 ns CMOS Input Test Waveform (CY7B9920) note 3 for variable definition. CY7B9910 CY7B9920 CY7B9910 CY7B9920 Min Max Min Max – 85 – 85 – ...

Page 6

... JR Notes 10. Test measurement levels for the CY7B9910 are TTL levels (1 1.5 V). Test measurement levels for the CY7B9920 are CMOS levels (V Test conditions assume signal transition times less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 11. For all three state inputs, HIGH indicates a connection to V circuitry holds an unconnected input ...

Page 7

... Figure 4. Zero Skew and Zero Delay Clock Driver System Clock Document Number: 38-07135 Rev. *G Figure 3. AC Timing Diagrams t t REF RPWL t RPWH t ODCV t ODCV t t SKEW SKEW REF FB REF TEST CY7B9910 CY7B9920 t JR Load Z 0 Load Z 0 Load Z 0 Load Z 0 Page [+] Feedback ...

Page 8

... Operational Mode Descriptions Figure 4 on page 7 shows the device configured as a zero skew clock buffer. In this mode the CY7B9910/CY7B9920 is used as the basis for a low skew clock distribution tree. The outputs are aligned and may each drive a terminated transmission line to an independent load. The FB input is tied to any output and the operating frequency range is selected with the FS pin ...

Page 9

... Temperature Industrial X = Pb-free, blank = not Pb-free S = SOIC package Speed grade based on propagation delay Base part number 7B9910 = Clock buffer with TTL outputs 7B9920 = Clock buffer with CMOS outputs Company ID Cypress CY7B9910 CY7B9920 Operating Range   Industrial, – +85 C   ...

Page 10

... MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE MIN. 3. DIMENSIONS IN INCHES MAX. 4. PACKAGE WEIGHT 0.65gms * 0.394[10.007] 0.419[10.642] SEATING PLANE 0.092[2.336] 0.105[2.667] 0.004[0.101] * CY7B9910 CY7B9920 PART # S24.3 STANDARD PKG. SZ24.3 LEAD FREE PKG. * 0.0091[0.231] 0.015[0.381] 0.0125[0.317] 0.050[1.270] 51-85025 *D Page [+] Feedback ...

Page 11

... Voltage controlled oscillator Document Conventions Units of Measure Symbol Unit of Measure °C degree Celsius k kilohms MHz megahertz µA microamperes mA milliamperes ms milliseconds mW milliwatts ns nanoseconds  ohms % percent pF picofarads ppm parts per million ps picoseconds V volts Document Number: 38-07135 Rev. *G CY7B9910 CY7B9920 Page [+] Feedback ...

Page 12

... Document History Page Document Title: CY7B9910/CY7B9920 Low Skew Clock Buffer Document Number: 38-07135 Orig. of Submission Revision ECN Change ** 110244 SZV *A 1199925 DPF/AESA *B 1353343 AESA *C 2750166 TSAI *D 2761988 CXQ *E 2896073 CXQ *F 3010397 KVM *G 3047620 BASH Document Number: 38-07135 Rev. *G Description of Change Date ...

Page 13

... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07135 Rev. *G All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised October 7, 2010 CY7B9910 CY7B9920 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | ...

Related keywords