CY7B9920-5SI Cypress Semiconductor Corp, CY7B9920-5SI Datasheet - Page 3

• Manufacturer Part Number: CY7B9920-5SI
• Description: IC CLK BUFF SKEW 8OUT 24SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of CY7B9920-5SI

• Pll: Yes
• Input: Clock
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: No/No
• Frequency - Max: 80MHz
• Divider/multiplier: No/No
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Frequency-max: 80MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pinouts
Table 1. Pin Definition
Test Mode
The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910 and
CY7B9920 to operate as described in
have a removable jumper to ground or be tied LOW through a 100  resistor. This enables an external tester to change the state of
these pins.
If the TEST input is forced to its MID or HIGH state, the device operates with its internal phase locked loop disconnected and input
levels supplied to REF directly control all outputs. Relative output-to-output functions are the same as in normal mode.
Document Number: 38-07135 Rev. *G
Notes
REF
FB
FS
TEST
Q[0..7]
NC
V
V
GND
Signal Name
1. When the FS pin is selected HIGH, the REF input must not transition upon power up until V
2. The level to be set on FS is determined by the “normal” operating frequency (f
3. For all three state inputs, HIGH indicates a connection to V
CCN
CCQ
[1, 2, 3]
FB inputs are f
multiplication by using external division in the feedback path of value X.
circuitry holds an unconnected input to V
[1]
NOM
when the output connected to FB is undivided. The frequency of the REF and FB inputs are f
PWR
PWR
PWR
NC
IO
O
I
I
I
I
Reference frequency input. This input supplies the frequency and timing against which all functional
variations are measured.
PLL feedback input (typically connected to one of the eight outputs).
Three level frequency range select. The ranges are described in the switching characteristics
tables.
Three level select. See
Clock outputs.
No connect.
Power supply for output drivers.
Power supply for internal circuitry.
Ground.
Figure 1. Pin Configuration – 24-pin (300-Mil) Molded SOIC
CC
Block Diagram Description on page
/ 2.
V
V
V
V
GND
REF
CCQ
CCQ
CCN
CCN
NC
Q0
Q1
CC
Q2
Q3
FS
, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
TEST
MODE.
1
2
3
4
5
6
7
8
9
10
11
12
Top View
7B9910
7B9920
SOIC
NOM
) of the VCO (see
13
14
24
23
22
21
20
19
18
17
16
15
Description
1. For testing purposes, any of the three level inputs can
CC
reached 4.3 V.
GND
TEST
NC
GND
V
Q7
Q6
GND
Q5
Q4
V
FB
CCN
CCN
Logic Block
NOM
Diagram). The frequency appearing at the REF and
/ X when the device is configured for a frequency
CY7B9910
CY7B9920
Page 3 of 13
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