SI4133T-BM Silicon Laboratories Inc, SI4133T-BM Datasheet
SI4133T-BM
Specifications of SI4133T-BM
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SI4133T-BM Summary of contents
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... RFIPP Si4201- GND 1 15 SDO RXQP 2 14 PDN GND RXQN 3 13 XEN PAD RXIP 4 12 ION RXIN 5 11 IOP Si4133T- GND 1 21 GND IFLB 2 20 RFLA IFLA 3 19 RFLB GND GND 4 18 GND PAD VDD 5 17 RFLC GND 6 16 RFLD XIN 7 ...
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Aero 2 Rev. 1.4 ...
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... Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.6. XOUT Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 5. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 6. Pin Descriptions: Si4200-G- Pin Descriptions: Si4200DB- Pin Descriptions: Si4201- Pin Descriptions: Si4133T- .43 10. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11. Package Outline: Si4200-G-GM and Si4200DB- .45 12. Package Outline: Si4201- 13. Package Outline: Si4133T- Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Contact Information ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The Si4200 and Si4133T devices are high-performance RF integrated circuits with an ESD rating of < 2 kV. Handling and assembly of these devices should only be done at ESD-protected workstations. ...
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... Table 3. DC Characteristics (V = 2 – ° Parameter Si4200 Supply Current 1 Si4201 Supply Current 2 Si4133T Supply Current Total Chipset Supply Current 3 High Level Input Voltage 3 Low Level Input Voltage 3 High Level Input Current 3 Low Level Input Current 4 High Level Output Voltage ...
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... For pins SCLK, SDI, SEN, XEN, and PDN. 2. For pins CKN, CKP, ION, and IOP. 3. For XIN pins (Si4133T pin 7 and Si4201 pin 7). 4. The XSEL bit controls an internal divide-by-two circuit on the Si4201 and does not affect the XOUT pin. The DIV2 bit controls an internal divide-by-two circuit on the Si4133T ...
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PR 80% PDN 20% Figure 2. PDN Timing Diagram 80% D17 D16 SDI 50% 20 HOLD 80% SCLK 50% 20 EN1 CLK 80% SEN 50% 20% Figure 3. Serial Interface ...
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Aero Table 5. Receiver Characteristics (V = 2 – ° Parameter 1 GSM Input Frequency 1 DCS or PCS Input Frequency 2,3 Noise Figure at 25 °C 2,3 Noise Figure at ...
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Table 5. Receiver Characteristics (Continued 2 – ° Parameter 3,8 LNA Voltage Gain LNA Gain Control Range Analog PGA Control Range Analog PGA Step Size Digital PGA Control Range ...
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... Si4201 D/A converters. Offsets can be measured and calibrated out. See ZERODEL[2:0] in the register description. 11. Group delay is measured from antenna input to baseband outputs. Differential group delay is measured in-band. 12. Includes settling time of the Si4133T frequency synthesizer. Settling to 5 degrees phase error measured at RXIP, RXIN, RXQP, and RXQN pins. ...
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Receive Path Magnitude Response (CSEL = 0) 0 −20 −40 −60 −80 −100 −120 0 50 100 150 Figure 5. Receive Path Magnitude Response (CSEL = 0) Receive Path Passband Magnitude Response (CSEL = −2 −4 −6 ...
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Aero 0 −20 −40 −60 −80 0 Figure 8. Receive Path Magnitude Response (CSEL = −2 −4 −6 −8 −10 −12 −14 −16 0 Figure 9. Receive Path Passband Magnitude Response (CSEL = ...
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Table 6. Transmitter Characteristics (V = 2 – ° Parameter 1 RFOG Output Frequency 2 RFOD Output Frequency 3,4 I/Q Differential Input Swing 3 I/Q Input Common-Mode 3,4 I/Q Differential Input ...
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... Measured with pseudo-random pattern. Carrier power and noise power < 1.8 MHz measured with 30 kHz RBW. Noise ≥ power 1.8 MHz measured with 100 kHz RBW. 7. Measured with all 1s pattern. 8. Includes settling time of the Si4133T frequency synthesizer. Settling time measured at the RFOD and RFOG pins to 0.1 ppm frequency error. 14 Symbol Test Condition From powerdown Rev ...
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Table 7. Frequency Synthesizer Characteristics (V = 2 – ° Parameter 1 RF1 VCO Frequency 1 RF2 VCO Frequency 1 IF VCO Frequency RF1 PLL Phase Detector Update Frequency IF and ...
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... For the GSM input, the RF1 VCO is divided by two on the Si4200. During transmit, the IF VCO is divided by two on the Si4200. These tuning ranges are guaranteed provided the VCOs on the Si4133T are properly centered during the PC board design phase. See “AN49: Aero Transceiver PCB Layout Guidelines” for more information. ...
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... RFIPP VDD VDD 3 V C12 GND GND 2 20 IFLB RFLA IFLA RFLB GND GND 5 17 VDD RFLC 6 SI4133T 16 GND RFLD 7 15 XIN GND Rev. 1.4 Aero EGSM TX OUTPUT DCS/PCS TX OUTPUT Z1 EGSM RX INPUT OUT OUT+ GND C2 Z2 DCS RX INPUT OUT OUT+ GND ...
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... Murata LQW15A series (0402 size) Multi-layer (0402 or 0603 size) PCB Trace PCB Trace Silicon Laboratories Si4200-BM Silicon Laboratories Si4201-BM Silicon Laboratories Si4133T-BM EPCOS B39881-B7719-C610 (6-pin, 2.0x2.5 mm) EPCOS B39881-B9001-C710 (5-pin, 1.4x2.0 mm) Murata SAFSD881MFL0T00R00 (6-pin, 2.0x2.5 mm) Murata SAFEK881MFL0T00R00 (6-pin, 1.6x2.0 mm) EPCOS B39941-B7721-C910 (6-pin, 2.0x2.5 mm) EPCOS B39941-B7820-C710 (5-pin, 1 ...
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... RF and IF VCOs, varactors, and loop filters. The unique integer-N PLL architecture used in the Si4133T produces a transient response that is superior in speed to fractional-N architectures without suffering the high phase noise or spurious modulation effects often associated with those designs. This fast transient ...
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... LNAG[1:0] and LNAC[1:0] bits in register 05h. A quadrature image-reject mixer downconverts the RF signal to a 100 kHz intermediate frequency (IF) with the RFLO from the Si4133T frequency synthesizer. The RFLO frequency is between 1737.8 and 1989.9 MHz, and is divided by two in the Si4200 for GSM 850 and E- 20 ...
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... TXVCO is centered between the DCS 1800 and PCS 1900 bands, and its output is divided by two for the GSM 850 and E-GSM 900 bands. The Si4133T generates the RFLO frequency between 1272 and 1483 MHz. To allow a single VCO to be used for the ...
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... I/O SCLK SEN Figure 15. Si4133T Frequency Synthesizer Block Diagram The Si4133T dual frequency synthesizer is a monolithic CMOS integrated circuit that performs IF and RF synthesis. Two complete PLLs are integrated including VCOs, varactors, resonators, loop filters, reference and VCO dividers, and phase detectors. Differential outputs for the IF and RF PLLs are provided for direct connection to the Si4200 transceiver IC ...
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... SELF PLL TUNE 4.4.1. Determining L EXT The center frequencies for the RF1, RF2, and IF VCOs in the Si4133T are set using an external inductance ( very important that L EXT designed to ensure maximum manufacturing margin for the desired VCO frequency tuning ranges. Because the total tank inductance is in the low nH range, the ...
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... SDO pin after writing the revision register with the address to be read. SDO is enabled when PDN = 0 on the Si4201 and when PDN = 1 on the Si4133T, allowing the SDO pin to be shared. Writing to any of the registers causes the function of SDO to revert to its previously programmed function ...
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... DAC Config 19h Reserved 20h RX Master #1 RXBAND[1:0] 21h RX Master #2 0 DPDS[2:0] 22h RX Master # 23h TX Master #1 TXBAND[1:0] 24h TX Master #2 FIF[3:0] 30h Si4133T Revision/Read 31h Config 32h Powerdown 33h RF1 N Divider 0 0 34h RF2 N Divider 0 0 35h IF N Divider 0 0 3Ah Reserved ...
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... Program to zero. Chip Reset Normal operation (default Reset all registers to default values. Note: See “5. Control Registers” on page 25. for more details. This register must be written to 0 twice after a reset operation. This bit does not reset Si4133T registers 30h to 35h. Rev. 1 ...
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Register 02h. Mode Control (Si4200/Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:3 Reserved 2 AUTO 1:0 MODE[1:0] Note: Calibration must be performed each time the power supply is applied. ...
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Aero Register 03h. Configuration (Si4200) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name DIAG[1:0] Bit Name 17:14 Reserved 13:12 DIAG[1:0] 11 SWAP 10:8 Reserved 7:6 TXBAND[1:0] 5:4 RXBAND[1:0] 3:2 Reserved 1 Reserved 0 Reserved ...
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Register 04h. Transmit Control (Si4200) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:11 Reserved 10 Reserved 9:8 BBG[1:0] 7:4 FIF[3:0] 3:0 Reserved BBG[1:0] ...
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Aero Register 05h. Receive Gain (Si4200/Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:14 Reserved 13:8 DGAIN[5:0] 7 Reserved 6:4 AGAIN[2:0] 3:2 LNAC[1:0] 1:0 LNAG[1: DGAIN[5:0] ...
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Register 10h. Revision/Read (Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:8 Reserved 7:0 REV1[7:0] Note: Registers on the Si4201 can be read by writing this register with the address ...
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Aero Register 11h. Configuration (Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:14 Reserved Program to zero. 13:11 DPDS[2:0] Data Path Delayed Start. 111= Use for GSM 850 and GSM 900 ...
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Register 12h. DAC Configuration (Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:11 Reserved 10 Reserved 9 XBUF 8 Reserved 7 ZDBS 6:4 ZERODEL[2:0] 3:2 DACCM[1:0] 1:0 DACFS[1: ...
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Aero Register 19h. Reserved (Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:0 Reserved Register 20h. RX Master #1 Bit D17 D16 D15 D14 D13 D12 D11 D10 Name RXBAND[1:0] ...
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... Note: See registers 04h and 35h for bit definitions. Register 30h. Revision/Read (Si4133T) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:8 Reserved 7:0 REV3[7:0] Note: Registers on the Si4133T can be read by writing this register with the address of the register to be read [15:0] RF2 [13: ...
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... Aero Register 31h. Main Configuration (Si4133T) Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name SDOSEL[3:0] Bit Name 17:15 Reserved 14:11 SDOSEL[3:0] 10:5 Reserved 4 RFUP 3 DIV2 2:1 Reserved 0 Reserved Function Program to zero. SDO Output Control Register. The mux_output table is as follows: 0000 Connected to the Output Shift Register (default) ...
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... Bit Name Program to zero. 17:16 Reserved N Divider for RF PLL (RF1 VCO). 15:0 N [15:0] RF1 Used for Receive mode. Register 34h. RF2 N Divider (Si4133T) Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name 0 0 Bit Name Program to zero. 17:16 Reserved N Divider for RF PLL (RF2 VCO). ...
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... Aero Register 35h Divider (Si4133T) Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name 0 0 Bit Name Program to zero. 17:16 Reserved N Divider for IF Synthesizer. 15:0 N [15:0] IF Used for transmit mode. Register 3Ah. Reserved (Si4133T) Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 ...
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... Register 3Fh. Reserved (Si4133T) Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name Bit Name Program to zero. 17:5 Reserved Program to one. 4 Reserved Program to zero. 3:0 Reserved Function Rev. 1.4 Aero ...
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... Clock input from Si4201 (differential). Transmit I input (differential). Transmit Q input (differential). IFLO Input from Si4133T (differential). Ground. Connect to ground plane on PCB. RFLO Input from Si4133T (differential). Supply voltage. Diagnostic output. Can be used as digital outputs to control antenna switch functions. PCS LNA input (differential). ...
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... Clock input from Si4201 (differential). Transmit I input (differential). Transmit Q input (differential). IFLO Input from Si4133T (differential). Ground. Connect to ground plane on PCB. RFLO Input from Si4133T (differential). Supply voltage. Diagnostic output. Can be used as digital outputs to control antenna switch functions. PCS LNA input (differential). ...
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Aero 8. Pin Descriptions: Si4201-BM Pin Number(s) Name 1, 8, GND GND pad 2, 3 RXQP, RXQN 4, 5 RXIP, RXIN 6, 20 VDD 7 XIN 9, 10 CKP, CKN 11, 12 IOP, ION 13 XEN 14 PDN 15 SDO ...
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... Pin Descriptions: Si4133T-BM Pin Number(s) Name 14, 15, GND 18, 21, 22, GND pad 2, 3 IFLB, IFLA 5, 25, 28 VDD 7 XIN 9 PDN 10 SDO 11 SEN 12 SCLK 13 SDI 16, 17 RFLD, RFLC 19, 20 RFLB, RFLA 23, 24 RFLON, RFLOP RF PLL output to Si4200 (differential). 26, 27 IFLON, IFLOP GND 1 21 GND ...
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... Si4200DB-GM Dual-Band Aero Transceiver GSM 850/PCS 1900 or E-GSM 900/DCS 1800 Si4201-BM Universal Baseband Interface Si4201-GM Universal Baseband Interface Si4133T-BM Dual RF Synthesizer Si4133T-GM Dual RF Synthesizer *Note: Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. 44 ...
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Package Outline: Si4200-G-GM and Si4200DB-BM Figure 18 illustrates the package details for the Si4200-G-GM and the Si4200DB-BM. Table 11 lists the values for the dimensions shown in the illustration PIN1 ID 0.50 DIA ...
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Aero 12. Package Outline: Si4201-BM Figure 19 illustrates the package details for the Si4201-BM. Table 12 lists the values for the dimensions shown in the illustration PIN1 ID 0.50 DIA Top View Figure 19. ...
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... Package Outline: Si4133T-BM Figure 20 illustrates the package details for the Si4133T-BM. Table 13 lists the values for the dimensions shown in the illustration PIN1 ID 0.50 DIA Top View Figure 20. 28-Pin Quad Flat No-Lead Package (QFN) Symbol Millimeters Min Nom A — 0.85 A1 0.00 0.01 A2 — ...
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... Added notes 5 and 6. "12. Package Outline: Si4201-BM" on page 46 Updated L dimension. Updated device weight. Added notes 5 and 6. "13. Package Outline: Si4133T-BM" on page 47 Updated D2,E2 dimensions. Updated device weight. Added notes 5 and 6. Revision 1.3 to Revision 1.4 Updated "10. Ordering Guide" on page 44 to include the Si4200-G-GM ...
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N : OTES Rev. 1.4 Aero 49 ...
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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and Aero are trademarks of Silicon Laboratories Inc. Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holder 50 Rev ...