SI5316-B-GM Silicon Laboratories Inc, SI5316-B-GM Datasheet - Page 8

• Manufacturer Part Number: SI5316-B-GM
• Description: IC PREC JITTER ATTENUATOR 36QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Jitter Attenuatorr

Specifications of SI5316-B-GM

• Number Of Circuits: 1
• Package / Case: 36-QFN
• Pll: Yes with Bypass
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 710MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 1.62 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 710MHz
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 19.38 MHz
• Output Frequency Range: 19.38 MHz to 710 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 1.71 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

*Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD).
Si5316
8
20*, 31
8, 19*,
Pin #
15
12
13
14
16
17
18
21
11
7
6
Pin Name
DBL_BY
CKIN2+
CKIN2–
CKIN1+
CKIN1–
RATE0
RATE1
GND
LOL
XB
XA
CS
GND
I/O
O
I
I
I
I
I
I
Table 3. Si5316 Pin Descriptions (Continued)
Signal Level
LVCMOS
LVCMOS
3-Level*
3-Level*
Analog
Supply
Multi
Multi
External Crystal or Reference Clock.
External crystal should be connected to these pins to use internal
oscillator based reference. Refer to Family Reference Manual for
interfacing to an external reference. External reference must be from
a high-quality clock source (TCXO, OCXO). Frequency of crystal or
external clock is set by the RATE pins.
Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. Grounding these
pins does not eliminate the requirement to ground the GND PAD on
the bottom of the package.
*Note: May be left NC.
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crystal or
reference clock to be applied to the XA/XB port. Refer to the Family
Reference Manual for settings. These pins have both a weak pull-up
and a weak pull-down; they default to M. The "HH" setting is not sup-
ported.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Clock Input 2.
Differential input clock. This input can also be driven with a single-
ended signal.
Output Disable/Bypass Mode Control.
Controls enable of CKOUT divider/output buffer path and PLL
bypass mode.
L = CKOUT enabled
M = CKOUT disabled
H = Bypass mode with CKOUT enabled
This pin has a weak pull-up and weak pull-down and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Clock Input 1.
Differential input clock. This input can also be driven with a single-
ended signal.
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator.
0 = PLL locked
1 = PLL unlocked
Input Clock Select.
This pin functions as the input clock selector. This input is internally
deglitched to prevent inadvertent clock switching during changes in
the CKSEL input state.
0 = Select CKIN1
1 = Select CKIN2
Must be driven high or low.
Rev. 0.4
Description